In many RAMs, if you read and write to the same address on the same edge, the read returns the old RAM contents, not the new one. So you have to bypass the RAM- you add a mux and a register to use the new data instead of the old if the addresses happened to be the same. In FPGAs, this bypass logic is sometimes automatically generated, depending on the coding style you used for inferred RAM.

This is in addition to bypassing the ALU stage.

So the computer architecture question is whether or not massive amounts of bypassing (with resulting slower fMAX) is worth it, vs. stalling. You need a representative test suite to answer this.