Is the RTL autogenerated from the chip images? I looked at one file 68k.v and the variable names remind me of a decompiler.
the genesis "specific" ym* cores look a lot more "authored"; commit history shows more activity around those files too
but thats just a guess... something that can generate verilog from chip images would be pretty cool...
Do we have tools for exposing specific layers instead of 2D images? It would, perhaps, be interesting to go with diagonal slices as we grind the chip and, aided by exaggerated vertical features, capture the full depth on a single pass.
- The X-Ray Tech That Reveals Chip Designs: https://spectrum.ieee.org/chip-x-ray