Comment by sbierwagen | Hacker News Reader

Comment by sbierwagen | Hacker News Reader

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It's also terribly inefficient. EUV "mirrors" eat 30% of the incoming light. Since they have such a narrow reflective range and the source light isn't collimated or coherent, you have to use a bunch of them. By the time you're at the mask, you've lost 96% of the light. As a result:

>Hynix reported at the 2009 EUV Symposium that the wall plug efficiency was ~0.02% for EUV, i.e., to get 200-watts at intermediate focus for 100 wafers-per-hour, one would require 1-megawatt of input power

https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...

It's an damn good question of how much further this can scale. EUV photons are a lot more like x-rays than they are visible light. They're energetic enough now they're inflicting ionization effects on photoresist material, blurring the exposed area with secondary electron scatter. The fundamental limit of electronic transistors, ones made out of single molecules, are going to be tough to make with lithography.

Still, 1 MWh is a tiny fraction of the power those 100 wafers worth of chips will consume in their lifetime. So if we can reduce power consumption with smaller features, it's worth using more laser power.

That makes me wonder (as someone who has merely heard of the two technologies and knows nothing much about either beyond the Wikipedia page) why it's not using a free electron laser?

Aren't those tuneable to any wavelength down to X-rays?

Global foundries banked on that, and a Japanese laboratory is building/running a demonstrator.

Isn't that similar to synchrotron x-rays? I just watched a video where they say that that's what people started with before they went with the tin plasma method.

It is somewhat likely that effective free electron laser is locked up behind the invention secrecy act of 1951 as a critical DOD tech.

Is it? And what is "effective? Tabletop? Deskside? Or this: https://www.xfel.eu/ ?

XFEL is

> Wavelength 0.05 to 4.7 nanometres

- https://www.xfel.eu/facility/overview/facts_amp_figures/inde...

which is sufficient and possibly excessive.

Not that I know anything about any of the other considerations in such things. Is 3.4 km "too big"? Is €1.22 bn "too expensive"?

Here’s a paper on some research in this direction:

https://iopscience.iop.org/article/10.35848/1347-4065/acc18c

That's called electron-beam lithography:

> This form of maskless lithography has high resolution but low throughput, limiting its usage to photomask fabrication, low-volume production of semiconductor devices, and research and development. [1]

The beam has to scan across the entire wafer instead of exposing it all at once, so it's extremely slow and uneconomical for mass production.

[1] https://en.wikipedia.org/wiki/Electron-beam_lithography

It's worth noting that necessity has tendency to make this possible though: the original CD laser diodes required extreme equipment investment to mass produce.

You could conceive of making the speed up in parallel production.

Or use an 8x8 array of them and have 64bits...err...beams at the same time.

IIRC you can't usefully do that, because the limit is from the combined electric field of the electrons in the beam(s) causing blurriness — more beams at fixed current per beam means more blur.

Treat it like a phased array, with hypermegamodulation by realtime machine learning artificial fuzzy logic, canceling out any blurriness in advance, producing the finest and sharpest turbonanoscalpels, able to etch any sketch, fast. Built to last!

F... yeah!

I'm fairly sure they're two different things: e-beam (as per your link) does the reaction with the electrons themselves, whereas FEL uses an electron beam as a lasing medium.

https://en.wikipedia.org/wiki/Free-electron_laser

The final challenge will be cost: With every iteration, costs increase dramatically. At some point, it simply ceases to make sense to scale down transistors any further.

Cost has been the challenge for the past 30-40 years at least.

Many semiconductor manufacturers have folded, dropped out, or merged over the years due to costs putting development of the next node out of their reach. If the remaining 3 drop out of the race, they will be following the same pattern as many before.

R&D and tooling costs have grown enormously to bring new fab process nodes online, but the actual per-wafer costs of materials and operating expenses historically haven't been growing to the same alarming degree. But that's changing, as new nodes are increasingly relying on power-hungry tools with low throughput that wear out mask sets at an unprecedented rate. It's not implausible for the industry to reach a point where new leading-edge processes will never mature to the point that they make economic sense for the low-cost applications that currently stay a few nodes behind the leading edge.

The problem here would be that if mask sets wear out at an unprecedented rate, it might not make sense to use these cutting edge nodes in the future (if/when we're several nodes ahead by then) for the things that currently use older nodes. Maybe Moore's law is dead for the types of things that stay 2 or 3 nodes behind state of the art all the time.

That was because of competition. The cost per transistor actually went down by a lot. If it soon goes up significantly, it will stop to make economic sense to increase transistor density any further. Why pay the same amount of money for a less powerful chip?

Maybe it will make sense for mobile SoCs or some other energy constrained applications which benefit from lower power draw of smaller process node chips. But power efficiency can outweigh lower absolute performance only to some degree.

> That was because of competition. The cost per transistor actually went down by a lot.

I'm not talking about the marginal cost to make the device, I'm talking about the R&D and capital expenditure to develop and build the machines for the next node.

You can be reductive and say it always boils down to competition, but then you would also say that ultimately shrinking will end when it can no longer compete with mature nodes. Competition in both cases. So I'm not sure what exactly that's getting at.

> If it soon goes up significantly, it will stop to make economic sense to increase transistor density any further. Why pay the same amount of money for a less powerful chip?

That's not strictly true, performance of a transistor still has value. Companies like Apple pay premiums to get in early on leading edge nodes, more per device than the mature nodes they move from.

Competition with "mature nodes" is different in the sense that here one company (like TSMC) will be "competing" with itself. They will just stop building next gen fabs if their chips wouldn't sell.

> That's not strictly true, performance of a transistor still has value. Companies like Apple pay premiums to get in early on leading edge nodes, more per device than the mature nodes they move from.

Apple can't increase the price of their product arbitrarily. So if the price per performance increases, the new iPhone would be slower than the old one. Maybe people will still buy it if it has better power efficiency, but that is a trade-off which has its limits.

> Apple can't increase the price of their product arbitrarily.

Not arbitrarily, but IIRC Apple's profit margin on iPhones is over 100% - the iPhone 14 Pro max is supposed to have a BoM cost of ~470 $ and retails for well over 1000$. That means Apple can both afford the high upfront premium/R&D cost of going to a smaller node and to eat up higher SoC costs and yet still have a profit per unit that would lead most other companies' CFOs to drool.

On top of that, even if the economics should not work out for mobile... a fully spec'd out M2 Ultra Mac Pro runs at ~14.000$, Intel ones IIRC could reach 50.000$. The crowd that pays such absurd prices has zero problems paying a grand or two more for higher performance.

> Competition with "mature nodes" is different in the sense that here one company (like TSMC) will be "competing" with itself.

No, why? Lots of foundries out there that don't compete on leading edge nodes.

> Apple can't increase the price of their product arbitrarily. So if the price per performance increases, the new iPhone would be slower than the old one. Maybe people will still buy it if it has better power efficiency, but that is a trade-off which has its limits.

That doesn't address what I said -- that price per transistor is not the single limiting factor. I never said any performance increase is worth infinite value.

> No, why? Lots of foundries out there that don't compete on leading edge nodes

The discussion was about Moore's law ("scaling down"), which is only about the leading edge.

The discussion moved to talking about is competing with mature nodes, where you said they'd only be competing with themselves (which doesn't seem to be right).

Well, it's right for the leading edge. The point is that they will stop scaling chips before technical limits are reached.

> Well, it's right for the leading edge.

No, the point was that the leading edge will stop advancing when it can no longer compete economically with companies that sell mature nodes. Which is obvious, but I was just being similarly reductive.

> The point is that they will stop scaling chips before technical limits are reached.

Sure, like most commercial ventures, cost becomes prohibitive at some point and overtakes benefits. As it always has been.

> No, the point was that the leading edge will stop advancing when it can no longer compete economically with companies that sell mature nodes.

The "mature node" here will just be the one before the first node that doesn't make economic sense anymore. And this will be from a leading edge company, most likely TSMC. Say, if 2nm is too expensive compared to 3nm, then TSMC will stick with 3nm.

Yep.

I’d note that quote is 14 years old - hopefully there’s been some R&D over that time!

Still, ASML's latest EUV machine, the 3600D, does draw 1.3 megawatts.

https://www.sec.gov/Archives/edgar/data/937966/0000937966220...

But when it comes to cost, evidently replacing many passes and other complicated processes with DUV machines with fewer EUV passes is a net win. And the energy required to create these chips must be a small fraction of the energy they will use in their lifetimes, so improved efficiency of the smaller nodes enabled by EUV would surely be a win, all else being equal.

I wonder what the possibilities for a fundamentally different manufacture method are. For example, what if we could program a layout into DNA and have biological agents construct it?

Well, unless one devises a way to break up atoms + rearrange those in such a way as to turn protons, neutrons, quarks etc. into compute machinery, we're stuck with individual atoms (or small groups of those) as the smallest possible building blocks. And thus Moore's law will hit a brick wall at some point. 3D structures (stacks w/ many layers of transistors & interconnect) will help, but make thermal issues more difficult than they already are.

Kind of like (iirc) the tip of a scanning tunneling microscope might be used to pick up & manipulate individual atoms.

Self-organizing materials like DNA might make that process easier, not scale it down further.

Read up on Molecular Nanotechnology.

Perhaps the thermal issues could be solved with LK99 :)

In other words, 10 kWh per wafer - a couple of dollars per wafer in energy costs.

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