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Comment by wheresmycraisin | Hacker News Reader

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wheresmycraisin·

Can anyone ELI5 this? Is it basically an emulator?

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Basically yes, but with the goal being semantic correctness rather than performance.

Seems to be similar to the official Sail model but F# instead of Sail.

Kind of funny since Sail can already compile to OCaml - probably wouldn't be too hard to add a F# backend. Then again, more independent implementations are always nice to have.

Would be interesting to know their motivation for this.

Edit: actually this looks like it has been dead for 3 years so maybe it was just a precursor to the Sail model.

https://github.com/riscv/sail-riscv

It's possible to emulate. But not only. The main goal is to formalize the representations of the RISC-V instruction set (ISA), decoder, executor, and state machine. So it's more formal point of view for RISC-V ISA.

> the RISC-V instruction set (ISA), decoder, executor, and state machine

So does this repo define these things as F# function and as a user I can import this repo as library and call those functions and my function call would directly run instructions on RISC-V processors, with no "middlewares" like operating system and such?

You can easily import and use specific functions for the decoder, or executor for specific ISA. Or even use the whole state machine. And this is represented by tests. Those. any single RISC-V architecture instruction, or an entire program. Because it can be used as a cpu emulator. Those. OS doesn't matter in this case. However, I draw your attention to the fact that this is only a processor, and not an emulation of the PC and its peripherals.

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