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Comment by muricula | Hacker News Reader

It seems like most of these new instructions and registers correspond to the original armv8 base isa. I'm going to go out on a limb here and suppose that's not an accident. Does anyone know why Intel thinks x86 needs them?

Is the goal here to increase the decode bandwidth of Intel CPUs?

Is the goal to reduce demands on load-store units by increasing the number of registers?

Are they hoping to make it easier to port or JIT armv8 asm to Intel CPUs?

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Most new instructions are not inspired by Armv8, they just implement the traditional 3-address format for 32 registers, which predates Armv8 by a few decades.

Nevertheless, there are a few instructions inspired by Armv8, mainly PUSH2 and POP2, which correspond to the load register pair and store register pair of Aarch64.

The new CCMP conditional-compare instruction is also equivalent to ARMv8’s instruction of the same name. If a condition passes, compare two registers; if not, set the condition bits to an arbitrary value.

On ARM that instruction is a pain in the ass when reading disassemblies, because the on-fail condition bits are just specified as a number from 0 to 15; the disassembler doesn’t bother to label which bits are specified, let alone what conditions they correspond to. Unfortunately it seems like Intel is doing the same thing in their assembly syntax, at least if I’m reading the document correctly.

well given the difficulty of making wider x86 decoders it does seem pretty reasonable to try reducing the number of load/stores needed

yeah, exactly. instruction fusing can turn mov+op2 into 3-reg operation, or push+push into push2. but adding new instructions allows to increase the frontend throughput too.

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