The future of computers: 3D chip stacking

I wonder if you could etch channels for liquid coolant directly into every 3rd layer or so...

You would reduce mean distance between all components and, depending on the graph of connections, save a lot on resistance losses.

But what about servers ? memory bandwidth is the biggest problem facing servers, and stacking solves it nicely.

And when you put chips side by side like xilinx's new chip, the heating issue is solvable.

I expect that what we'll see is a top layers of general purpose processing on top next to the heat sinks, then lower power layers further down, like maybe a layer of L3 cache then a stack of main memory. Probably also a lot of dark silicon which is only lit up for special tasks, like media encoding or encryption.

The A4 does use this technology, but Apple certainly did not invent it (though I wouldn't be surprised if they claimed so). It has been used in cell phones for years, and only recently others are starting to adopt it, and extend it to place two chips side by side on a Si substrate within a single package. The reasons are purely economical. In the past, much benefit can be had just by shrinking the transistor size. At the current feature sizes, though, physics is not helping anymore and there is very little benefit in terms of raw transistor and wire speeds, and power. So chip makers need to find more ways to extend Moore's law a few more years. FinFETs and stacked chips are just such ways.

TSV die stacking, wire-bond die stacking, and package-on-package chip stacking are different technologies with different costs and benefits. TSV stacking allows a massive number of wires between the layers, increasing bandwidth far beyond other types of stacking; of course, this comes at very high cost.

Also, PoP stacking was used in mobile SoCs long before the A4.