I'd love to see a RISC-V SoC (not just a dinky little MCU) that has real / complete documentation. So far I have yet to find any for any of the various RISC-V based SBCs that have shipped.
I'd love to see a RISC-V SoC (not just a dinky little MCU) that has real / complete documentation. So far I have yet to find any for any of the various RISC-V based SBCs that have shipped.
Was the idea of an open ISA leading to an open SoC was just wishful thinking?
RISC-V (and SiFive) caught a moment where it could be used is a way to squeeze ARM on pricing. It doesn't really meaningfully create openness on the interesting parts of the stack (core architecture, SoC architecture, etc.) on its own. In that sense, the hype is overblown.
It does _enable_ open-source cores to some degree, but that's it, someone has to take the leap to make a production-ready one. A few companies are trying, but an open-source SoC is even further down the road.
https://github.com/T-head-Semi/openc910
The same cores are used in the 64 core SG2042 workstation/server SoC.
RISC-V was sold to us as the fully open CPU ecosystem but all it offered was an open design and some reference implementation in Chisel. That is not much different from MIPS which opensourced some CPUs 10-15 years ago.
A lot more is needed for a fully open RISC-V computer.
It simply allows for open source implementations to exists.
> but all it offered was an open design and some reference implementation in Chisel
You are confused between what RISC-V the foundation and what different people in the ecosystem do. RISC-V was started by Berkley and then they created a foundation. There are NO REFERENCE Implementation! Not in Chisel or anything else. Chisel is simply what Berkley used for some of their initial work.
And it has largely worked. There are lots of high quality open CPUs. This was certainty not the case in the past:
- https://www.openhwgroup.org/
- https://www.chipsalliance.org/
There are many more.
> That is not much different from MIPS which opensourced some CPUs 10-15 years ago.
Its very different because you were not allowed to use those MIPS chips or built products with it. The only one that was as open was SPARC 32-bit.
What we don't have is cheap mass produced SoC that are well documented. But that a general problem of the industry not just RISC-V.
The boot process for RISC V is standardised. There are going to be far more RISC-V SBCs that support uefi than ARM SBCs.
ARM addressed this by creating ATF which most companies now use:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
I find the most useful there is the JH7110 TRM specifically.
There's links to a bunch more over here[1].
0. https://doc-en.rvspace.org/
1. https://forum.rvspace.org/t/visionfive-2-faq-quick-links/137...
As far as I can see, the only thing that isn't documented is the DDR startup/training code, which is a binary blob in u-boot. There are a few registers that are undocumented which need to be set to start up but I think the rest is well documented.
https://www.sifive.com/documentation
In addition to a documented RV64 SoC, it'd be cool to see some RV32 MCUs that are a little beefier -- more competitive with the mid-range Cortex M4 and M7 stuff (more peripherals, more SRAM, etc) -- instead of the existing stuff that looks similar to very tiny M0/M3 devices.
I find the most useful there is the JH7110 TRM specifically.
There's links to a bunch more over here[1].
0. https://doc-en.rvspace.org/
1. https://forum.rvspace.org/t/visionfive-2-faq-quick-links/137...
Last time I wanted rs-232 specs of a solar inverter, took me months to contact them and after some persuasion, a guy emailed me an NDA I had to physically print, sign, scan and send them back before they gave me a copy.
Obviously I was feeling funny so I signed Johnathan doe and they send me the file.
Turns out, that file was readily available online in forums because others had done the same thing.
So much for NDA. Sigh
Their proprietary driver will stay closed, but hopefully they'll be able to deprecate it at some point.