Teardown of the TM4313 GPS Disciplined Oscillator
tomverbeure.github.io
tomverbeure.github.io
...at least that's my best guess.
I've studied quite a bit of GPSDO schematics, but none of them are using the internal Vref. Though that maybe because these designs allow for different OCXOs, some of which don't have a Vref output.
"Lastly, I'm not going to use the Oscilloquartz reference voltage to power the frequency setting circuit. It seems the logical thing to do, but this so called reference voltage is anything but a reference voltage. They are typically created by using a zener (reference) diode like the TL431, but that is simply not good enough as you will see."
In some industrial GPS receivers, there was a FPGA, a very capable ADC, and a PLL. Logic was split between the analog incoming section and the digital processing section. Maxim components were used frequently as it they had excellent engineering support (sampling esp.) from the vendor. IIRC, there were Flash EEPROMs rated for 10k block writes (only!) but were reliable up to low 100k's.
PS: Alum of Trimble Nav Ltd radio group.
I only narrowly managed to escape this fate after acquiring an HP 5345A, a massive fifty pound brick that was the fastest (and thus accuratestest) reciprocal counter for some time. It's a pretty strong black hole for money.
There is hope.
They almost certainly implemented a digital PLL in the micro that compares the 10 MHz clock signal to the 1 PPS output of the GNSS module. Using a frequency lock would lead to a residual drift with respect to the GNSS time scale.
E.g. when using a GPSDO to drive or calibrate frequency counters, spectrum analyzers, signal generators, and similar kind of equipment.
There are many GPSDOs out there that are FLL only.
I'm not sure how you'd implement a pure digital-only phase detector inside an LPC1752. The precision of measuring the phase would be pretty terrible when the internal clock is only, say, 100MHz?
Edit: I should be able to check this by putting the GPS module 1PPS and the GPSDO 1PSS output on the scope.
> The LPC1759/58/56/54/52/51 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.
Time-tagging the transitions of the 1PPS signal (and subtracting 100000000 at each transition) directly gives the phase difference measured in clock cycles. At 100 MHz clock frequency, the resolution is 10 ns which is well below the timing jitter of a GNSS 1PPS output. The OXCO can then be steered using a very slow feedback loop (in order not to spoil its short-term stability).
I thought that 10ns was too coarse, when most PLL-based GPSDO get much higher accuracy with 8-bit ADCs. But maybe that just doesn't matter enough when the input jitter is very high to begin with.
Even the simplest TCXO is more stable than the GNSS up to a few ten s. The OCXO has the crossover at a few hundred s, and the Rubidium atomic clock at over one thousand s.
At these time scales, the jitter of the 1PPS measurement averages out very well and should not be a serious limitation.
A 100 MHz clock has a 10ns step size, and if you measure one cycle of the 1PPS signal, that 10ns of noise is 10 parts per billion.
But if you instead measure 100 cycles of the 1PPS signal, the same 10ns of noise is only 0.1 parts per billion.
I understand that you can still implement a PLL with a pure digital 10ns counter (I've once designed one to create a 12.288MHz I2S clock out of a very jitters 48kHz audio sample tick), but I'm wondering what the benefits are of using the analog interpolator.
If the input 1PPS signal is so jittery, when do you get diminishing returns in increasing the precision of the pulse-to-pulse measurement?
I own a more expensive GPSDO model from the same vendor and I can confirm that the TIC output is at 10ns resolution. TM4313 is being sold at 1/3 price of mine, I'd be very surprised if its TIC has a higher resolution.
Does anyone know whether I can use a GPSDO with an SDR to have very accurate timestamps of each I/Q sample? I don't just want the sampling to run at the correct phase, and without drift, I want a timestamp. Could be any SDR, but I'd prefer something reasonably priced (under $1000). Most SDRs will happily take the 10MHz reference clock, but are not be able to ingest or output time.
On the other hand, BladeRF has an FPGA on board, perhaps it can ingest PPS. It will still be quite a bit if work to write for the FPGA, but at least I'll not have to design PCBs, which is way above my skill level.
If you have a device that can record multiple bands simultaneously, and preserve timing between them, then you may be able to record both your target band and the GPS band and then use software later to reconstruct the time out of the GPS recording.
See: https://www.rtl-sdr.com/rtl-sdr-tutorial-gps-decoding-plotti...
(I always thought RS422 for the PPS signal is a bit fishy, not sure how jitter-y those transceivers are. That said the hardware I've seen uses >25Mbaud high-speed transceivers [ISL3180, THVD1452], maybe those are fine in that regard.)
A modern 5G base station kinda does what you describe. All SDR these days anyway :)
On LPC1752, it is actually up to 32 bits, if you are willing to wait that long for the period to tick over