Samsung Foundry Tracking 2nm In 2025 | Hacker News Reader

Samsung Foundry Tracking 2nm In 2025

semiwiki.com

71 points11thEarlOfMar38 comments

>TSMC overwhelming won the 3nm node with the N3X process family, however, the 2nm node is undecided. TSMC N2, Intel 18A, and Samsung 2nm are very competitive on paper and should be ready for external customers in the same time frame. It will all depend on how the PDKs proceed. According to the ecosystem, customers are looking at all three processes so it is a three horse race which is great for the foundry business. No one enjoys a one horse race except for that one horse.

Seems like there's huge fight for 2nm, there are billions of dollars on the stake after all

And it will be a relief to have an option at the leading edge.

Correct me if I’m wrong, but 2nm etc haven’t actually meant anything except “generation” for some time (except going down by 1 instead of up for marketing purposes).

So do they have a plan for 2 generations from now with respect to naming or are they really going to start marketing 0 or negative “nm” nodes?

Perhaps they'll change the acronym

It's only the press clinging onto this - TSMC themselves refer to it as N3B, N3E, N6/N7 etc, Intel's process is 10ESF or Intel 7, all without putting the "nm" there.

It's still useful to roughly group different foundry processes, but nobody who is actually paying the $100mm++ to use these processes is relying solely on rough grouping.

non-integral real numbers exist

And there was a time when we used them in the not-too-distant past! In the '80s, processes were all in microns, not nanometers. In the '90s nodes were described as 'sub-micron' and 'deep sub-micron' processes. It wasn't really until around 0.13u/130nm (early 2000s) when it became common to say "one-thirty nanometer" instead of "point one three micron".

I doubt anyone will actually have a problem saying "one point five nanometers" (or whatever) for the next node.

Intel is already using 18A (Angstrom).

It’s “18 Å”, not “18A” (which would be 18 Amperes). I would think that Intel would be keen to not be confused with either Ampere Computing or Nvidia’s Ampere GPU architecture.

People don't know how to type accents though.

It's dang easy on Mac. You just hit alt + the key it looks similar to.

Å = opt (AKA alt) + shift + a

Doing that for all of a..z and A..Z gives

å∫ç∂´ƒ©˙ˆ∆˚¬µ˜øπœ®ß†¨√∑≈\Ω

ÅıÇÎ´Ï©ÓˆÔ˚ÒÂ˜Ø∏Œ®Í†¨√∑≈ÁΩ

How would I know in advance that this gives Å and not Æ or Ã or Ā or Â or À or Á or Ä? And how would I type the other ones? Don't have a Mac, so I actually don't know how it is supposed to be done.

> How would I know in advance that this gives Å and not Æ or Ã or Ā or Â or À or Á or Ä?

The same way you know in advance that CTRL+SHIFT+@ gives you Å in Windows?

Both Windows and Mac can display an on-screen keyboard that will display the character that will be output if you press a key along with modifier keys like CTRL or Option.

That's a very US-centric view of things.

On my Mac pressing "opt (AKA alt) + shift + a" gives me: Ą - which I much prefer, since it comes from my native language :)

Intel calls it 20A/18A (Angstroms) instead of 2nm and maybe the next node will be something like 13A.

Does that have physical correspondence to anything? Smallest gap between units is 1.8-2nm?

It used to refer to the smallest feature they were able to print, not gate length. I don't even think it has a physical meaning anymore, hence why the fabs mostly dropped the nm suffix from their naming schemes.

It doesn't correspond to any physical size and hasn't for a while. The idea is that a sqrt(2) reduction in the marketing number is supposed to correspond to a significant increase in density and transistor performance.

Not at all. It used to back when transistors were planar and their distance could be measured in nm, but now transistor gates are 3D and we're just lowering the number to what the equivalent performance might be if a theoretical transistor gate were that small.

My understanding is that it's anything but a winner-takes-all race. If anything, the lack of capacity at the top means that all of the major fabs are likely to be booked solid ahead of time by the big silicon design corps like Apple, NVIDIA, and AMD.

Think about how insane the demand is about to be for whatever NVIDIA calls their 2nm generation AI accelerators!

What's fabbed by Samsung? Almost nothing these days. Companies won't use Samsung even when there's a TSMC shortage.

Previous Nvidia gen was on Samsung silicon iirc.

A100 was TSMC N7[1]; only consumer Ampere was Samsung 8N.

[1] https://developer.nvidia.com/blog/nvidia-ampere-architecture...

"only" for one of their best selling series.

The story underlying "best selling series" is buried in details that your 1-liner quip conveniently ignores.

To close FY23, Nvidia reported[1] -27% YoY gaming segment revenue decline, while data center segment saw +41% YoY revenue growth to overtake gaming segment revenue contributions by 65%. -8% YoY gross margin contraction was largely attributed to $2.17 billion Ampere inventory glut in excess of demand expectations.

Take a wild guess which segment accounts for the lion's share of this Ampere inventory glut.

[1] https://www.sec.gov/Archives/edgar/data/1045810/000104581023...

Samsung foundries cannot compete with TSMC on capacity. Regardless, they do have Nvidia and Qualcomm as customers.

I think the issues Qualcomm had at Samsung before moving to TSMC were performance and power based in addition to early yield issues.

https://www.anandtech.com/show/17395/qualcomm-announces-snap...

https://www.sammobile.com/news/samsung-foundry-4nm-yield-sna...

Samsung fabs a lot of memory. You can call it less sexy than a logic chip, but between nand and ram there's a lot of it going around.

These time lines are aspirational and are rarely met.

What's the situation of Intel 4? If they miss year end deadline, 20A should also be late.

Intel 4/3/20A/18A are Schrodinger's processes; there's no evidence they're on time (remember Intel has lied before) and there's no evidence they're delayed. If Meteor Lake ships in volume this year it will prove that 4 works.

Like the 10nm node, it was always coming for roughly 7 years till it wasn't.

But Intel jumped on the 7 node so even if 4 fails doesn't mean 2 will do as well.

Please use Å when referring to ångström. A is ampere.

Intel's given name for the process is 20A. It may hint towards Å but ain't officially that.

Silicon's atomic size is about 0.2 nanometers. What's the plans once single-atom transistors hit the shelves? Anything we can do to keep "Moore's Law" going?

Money is what keeps it going, if you just want to look at the # of transistors. The problem is that the advantages of modern process "scaling" have stopped being advantageous except for a few uses, and profitable for very few (one) producers. That will shrink investment in new Fabs. We may be at the last hurrah, unless something (AI?) really pops to keep demand up for more expensive transistors, or there's more government subsidy.

As a fundamental scaling law Dennard (supporting Moore) has already collapsed. Speed stopped scaling with node in the early 2000s, Power stopped in the mid 2000s, and cost per transistor before 2020. Cost per transistor is really critical, because you have to justify more complex designs when they aren't actually cheaper to make (as they have been every year for over 50 years).

   https://en.wikipedia.org/wiki/Dennard_scaling
   You used to get -50% cost&area reduction, -50% power reduction, +40% performance
   For each node (0.7x dimension scaling).

From the article, "Samsung’s 2nm (SF2) process has shown a 12% increase in performance, a 25% increase in power efficiency, and a 5% decrease in area, when compared to its 3nm process (SF3)." Estimates on cost/transistor are ~50% increase for SF2 due to layer count, yield, and production costs. The biggest improvement in transistor cost is now Fab amortization, but that only counts if the Foundry is overall profitable in the first few years. Otherwise, it's just a sunk cost born by stockholders, banks, and governments.

There's lots of other stuff like die/wafer stacking and more complex multi-chip modules (including optical/RF), but those all add significantly to complexity with marginal cost improvement. You need the payoff to be obvious or the bean counters stop giving you beans. So far momentum is carrying the investment, but a failure (eg Intel) could really cut that off.

Looking forward to 0nm in 2027

Reply on news.ycombinator.com