Modern mobile phones essentially have everything except memory and storage in a single chip, the Northbridge died a decade ago, and recent Zen chips can even function without a Southbridge.
Does this mean the processors have built-in USB and PCI controllers? Or is this more a case of "if you don't need many peripherals, you can do without a southbridge"?
I suspect the reason they can do without the southbridge is because many high-speed connections are PCIe these days (including storage and networking). But I don't see a good reason why Zen would have on-chip USB or RS232 controllers.
AM5, I don't know.
Socket AM5 has an integrated x16 PCIe bus, three x4 PCIe buses (one usually used for the chipset, one for NVMe, and one for USB4 ports - but other assignments are of course possible), a dedicated DisplayPort connection, a three-port hybrid USB3/DisplayPort interface, a dedicated USB3 connection, SMBus & I3C, and a HDA/SoundWire connection.
The AM5 Southbridge is essentially just a PCIe hub combined with some PCIe-to-USB and PCIe-to-SATA interfaces. If you don't need those, you can just leave it out! In practice you'll virtually always have it for the SATA ports and extra PCIe lanes, though.
Don't forget that USB is also a high-speed connection these days. 10Gbps is very common, and USB4 goes up to 40Gbps in Gen3 - with 80Gbps for Gen4 on the way. RS232 is indeed not included, but that's pretty much a dead port anyways: no reason to use it for onboard peripherals, and consumer motherboards rarely have a header for it these days.
i.e. CPUs need to be huge to achieve their performance targets, but wafer defects make for poor margins with chips that large, so they split up into chiplets to allow mixing and matching of good parts.
But SOCs are nowhere near that limit yet, so their tiny dies are growing to bring more more functionality on-die and reap the benefits of integration.
I wonder if that's it; simply keeping a PCIe link awake between various chips uses a bit of power to drive the trace capacitance, for instance.
It’s all volatile storage with different uses.
Is there a good overview of how much of a benefit the onchip ram is?
Intel already launched a processor with 16GB on-package MCDRAM in 2016 (Knight's Landing Xeon Phi). You can even buy an Intel Xeon with 64GB HBM2 today. Nvidia likewise has been packaging HBM with their server GPUs.
Embedded DRAM (eDRAM) been used for long time in the mobile and console space. e.g. IBM's POWER7 (e.g. Nintendo Gamecube) and Intel Haswell products. However, using a logic process node to make DRAM cells is wasteful. Packaging technologies have advanced sufficiently that you now regularly see regular DRAM dies (LPDDR, HBM) being put on-package.
But all of that is packaging and manufacturing technologies. We're still taking to DRAM over a memory bus like we're still living in the '80s. The true innovation I'm looking out for is for a company to stick its neck out and use a different communication standard to talk with the DRAM modules. Something like the CLX.mem standard, which is used in the server space to talk to memory expansion modules.
The amount of people that need memory speeds and latencies beyond what SO-DIMM and CAMM can handle, but only need 16GB of RAM is absolutely tiny.