TSMC Expected to Charge $25,000 per 2nm Wafer
tomshardware.com
tomshardware.com
Size Cost/Wafer % Increase
---- ---------- ---------
10nm $5,992
7nm $9,346 55%
5nm $16,988 81%
3nm $20,000* (est.) 17%
2nm $25,000* (est.) 25%
That was my oldest comment I could find on HN made in 2017. Although my projection was made on Anandtech some time around 2016.
I was originally projecting a slow down to 3 years cadence post 5nm at 3 / 2nm. But at the time there were no "Trillion Dollar" company and AI wasn't a thing. I was also at the time ignorant of HyperScaler's volume.
Even if all of that will allow us to go further, 2nm in 2025, 1.4nm in 2027 and 1nm in 2029 / 2030. Surely the hypotheses remains, that at some point the market will not be able to justify the cost of new node. And will have to amortized over a longer period of time.
At 1nm, if it were to cost $30K per Wafer, a 100mm die would cost $50 at 100% yield. That is excluding the potential $2 - $3B design cost.
Size Cost/Wafer % Difference
==== ========== ============
5nm $16,988
2nm $25,000 47%
Size Cost/Chip % Difference
==== ========== ============
5nm $238
2nm $350 47%
It's also worth mentioning that none of the big players will be paying sticker price. They negotiate contracts that pay per KGD (known good die) since the process yields are abysmal for the first year or two.
Intel is set to launch Meteor Lake on Intel 4 later this year or early 2024. That will put AMD and Intel on a similar process-level footing. If Intel can get Intel 20A out the door around the same time TSMC gets 2nm out the door, we might see Intel overtake AMD on process. Intel's latest roadmap has 20A in the "2023-2024" time frame which seems a tad unlikely at this point and 18A for "2024+". It's possible that Intel will get ahead of TSMC on process if they actually hit their roadmap given that TSMC is looking at 2025 for 2nm. In that case, AMD might be facing a tough battle.
If Intel can control its costs better than TSMC's charges, that will make a big difference. If TSMC's charges for 2nm are going to be 75% more than 5nm, that's going to eat into margins for someone like AMD.
However, while Intel does seem to be making some good moves today, it's probably too soon to completely buy into their roadmap. Yes, they're refocusing their culture in a positive direction. It's still reasonable to have some doubt on Intel's roadmap.
Who’s going to write a “Rosetta for Windows” that works seamlessly though?
Microsoft? https://learn.microsoft.com/en-us/windows/arm/apps-on-arm-x8...
> My frustration with this computer wasn’t a workload thing. It didn’t start out fast and gradually slow down as I opened more things and started more processes. It was peppered with glitches and freezes from start to finish.
I’d have only Slack open, and switching between channels would still take almost three seconds (yes, I timed it on my phone). Spotify, also with nothing in the background, would take 11 seconds to open, then be frozen for another four seconds before I could finally press play. When I typed in Chrome, I often saw significant lag, which led to all kinds of typos (because my words weren’t coming out until well after I’d written them). I’d try to watch YouTube videos, and the video would freeze while the audio continued. I’d use the Surface Pen to annotate a PDF, and my strokes would either be frustratingly late or not show up at all. I’d try to open Lightroom, and it would freeze multiple times and then crash.
https://www.theverge.com/23421326/microsoft-surface-pro-9-ar...
The other bulk of thr market is mobile, which is almost entirely arm already.
You're talking about the 2011 version of Rosetta that allowed Intel Macs to run PPC software.
>QuickTransit was a cross-platform virtualization program developed by Transitive Corporation. It allowed software compiled for one specific processor and operating system combination to be executed on a different processor and/or operating system architecture without source code or binary changes.
On the compatibility side, Boot Camp is less useful when Windows on Arm does its own x86 emulation and works well enough in Parallels. On the graphics side they wrote their own DirectX 12 wrapper. If they can port some AI libs over, running them on 64 GB of shared CPU/GPU memory would be pretty amazing.
Maybe in 10 years, if Intel generationally leapfrogs them again like with the PowerPC era. But short of that, what would they have to gain?
Of course, we'll have to see if Intel keeps up after finally clearing its 10nm hurdle.
The M series isn't as great as it seemed. It had an initial advantage of a smaller node, and benefits from everything being on-die. It's huge, so it relies more on the chip tech getting smaller than traditional CPU solutions.
They didn't have much choice. Apple booked most of the production capacity for those two years:
https://www.notebookcheck.net/Apple-secures-80-percent-of-TS...
The Ryzen 7940HS, which is a pretty good value, is on TSMC 4nm, rumored to already cost close to $20k/wafer.
Even if they double the transistor count, a single SKU should theoretically be cheaper to produce, since you're reducing the footprint by 4. Of course, this is assuming yields don't fall too badly on 2nm (which they probably will, 2nm feels like alien technology at this point).
TSMC N2 is estimated to be something like 30% denser than N4.
I'm curious if the price increase isn't as bad as it seems because of that, but IANAE.
In any case, I suppose this was expected. TSMC is on the bleeding edge of technology, and the techniques and equipment that make all of this possible is absurdly astounding. It's a miracle of modern cooperation and science that any of it works at all.
Prices will go down as the process matures, and we all see progress march forward. Win-win to me.
Take RDNA3 as an example. Even if you get 100% yields, you need a significant amount of additional area in the product. N31 is over 500mm2 of area even if it's yielded as a 308mm2 chiplet and six 38mm2 chiplets. Even if all of those yield at 100% you can't make it not be 500mm2 of area, and you have to pay for that.
And because MCM imposes some performance overheads that have to be compensated for, and because of the innate nature of the additional PHYs taking up area, the actual total area is larger than a monolithic chip. This is an offsetting factor in the comparison to monolithic, yes monolithic yields lower but it also needs less actual silicon too, and that pushes yields back up a touch and pushes wafer cost down a touch.
Comparisons between products are always inexact, and NVIDIA is on a slightly different node (a customized version of N4/N5P called 4N) but it's the same general family (AMD is on N5P) and 7900XTX is using 531mm2 total to compete with the 4080 which uses only 378mm2 - so we are talking about potentially a 40% area overhead for MCM, which is significant in terms of increased wafer cost even if the yields are higher.
Even if you assume RDNA3 missed expectations and "should" have performed somewhat better... we are still probably talking about a >20% area advantage for monolithic products.
https://en.wikipedia.org/wiki/List_of_AMD_graphics_processin...
https://en.wikipedia.org/wiki/List_of_Nvidia_graphics_proces...
(and, note that rumors have swirled recently that N4 and N5P are actually the same thing, they have the same density and library. Reportedly, both TSMC and Samsung faked their N4 and 4LPX libraries for marketing reasons and pushed the "true" node off, in the same way that TSMC kinda pushed off the real N3 into N3E (e for enhanced) and called the shitty version N3B (b for bad) instead... so N4 vs N5P for the basis of the 4N custom nodelet may not actually be a meaningful distinction after all, lol. And RDNA3 and Ada may actually be on the same parent node as a result.)
https://www.reddit.com/r/hardware/comments/145e9ft/tsmc_n4_i... (actual tweet seems to be removed?)
Anyway, it is the same thing in CPUs too - yes, the CCD/IO die approach is great, but, it also does use a lot more silicon than a monolithic chip would for an equivalent design. Epyc has 8 or 16 chiplets of N5P and another giant chiplet of N6 for the IO die. That's a lot of total area, and wafer costs continue to increase.
The other place it bites is in GPU dies too. PHYs don't shrink, and there are de-facto "minimums" of 4 PHYs per GPU (of any performance) imposed by actual raw bandwidth requirements and the need for 8GB of VRAM (current max is 2GB/16gbit per module unless you go clamshell, which drives up cost a ton). Every time you shrink, the wafer cost of that fixed, non-shrinkable PHY area goes up by 25% or 50%, even if you yield that area at 100%, and the performance does not increase accordingly. This is what's been eating up the gains in the low-end dGPU market, and this is the reason AMD chose not to shrink RX 7600 / Navi33 to N5P with the rest of the lineup and left it on N6 instead.
Thermals are the elephant in the room with stacking and wafer costs are the elephant in the room with MCM and PHYs. Yes, yields are better, but it doesn't mean the wafers are free either.
"The chart below is from Marvell’s 2020 investor day. The bar for 28nm was approximately 2011-2012."
Cost is per 100 million gates.
90nm - $4.01
65nm - $2.82
45/50nm - $1.94
28nm - $1.30
20nm - $1.42
16/14nm - $1.43
10nm - $1.45
7nm - $1.52
Most companies target the same die size across generations. For example, AMD CCDs have been close to 80 mm2 for three generations and Apple keeps the A-class die size around 100 mm2.
This says that the 5nm reticle size is 26mm x 33mm
https://fuse.wikichip.org/news/3377/tsmc-announces-2x-reticl...
If you are making a huge chip that is close to the max reticle size then you can't share it with anyone.
When I have done shuttle runs they split the reticle into 4x4mm sections and each cost about $100,000 in 28nm. I think the full 28nm mask set was a few million dollars back in 2012 when it was current technology. You could get another size in multiples of 4 like 4x8mm or 8x8mm where you paid another $100K for each 4x4 section.
But you can't use these shuttle masks when you are going to full production where you make millions of chips because you would be making chips from other company's next to yours and that company may have had bugs in that mask or only want 100,000 chips while you want a million.
The masks are a one time cost (assuming you don't have any bugs which is rare) but that is a huge portion of the NRE (Non Recurring Engineering cost or one time cost)
My question is, do they factor in a significant transisyor failure rate and silently reroute or something or are things actually stable enough to survive years of real world usage without transistor failure becoming an issue?
Is it possible to calculate a cost pr. usable transistor? And how does 2nm compare with its predecessors?
where is all this drive to smaller and faster and faster coming from? and why?
Some things werent possible with computational power of the e.g year 2000 and now are.
I mean… it is more capable, by a lot, and so are the current 14s.
The question is… do you use it? You may not. That’s fine. But some people do.
Not least the hardware can do more with less power. That’s pretty incredible. Plus faster graphics, memory, and cpu all improve overall responsiveness. That’s without going into the camera, neural engine, on chip image processing, etc.
These all improve with each generation. There is absolutely a difference, especially between a gap of 4 versions like you have.
But it’s ok that you don’t need it. Many other of us certainly do appreciate the improvements though!
Or to make another comparison. An 2016 MacBook Air was pretty mediocre-performance-wise and would require loud fans to spin up for a minimal amount of work. The 2020 MacBook Air M1 was about as fast in compiling Rust projects as a Ryzen 3700X (with 65W TDP), while being completely passively cooled and therefore quiet.
Also, incremental improvements are how we get from a big 4.77MHz XT to a supercomputer in your backpack. It's a bit akin to saying: I have a 4.77MHz XT and my wife an 8MHz AT and I don't really see the difference when running WordStar. The AT is an improvement over the XT, perhaps not noticeable for for some applications, but year-over-year improvements are needed to make big leaps over longer time periods.
As to the drivers.. performance, efficiency, consumer expectations, smaller devices such as wearable and IoT, and a competitive market where if you deliver on these you get a ton of consumers.
Your question could be posed to anything. Why does someone want a smaller battery? Perhaps they want their electric car to weigh 500 pounds less so it gets more range. Why didn't we stop when computers were the size of buildings?
I can't think of any apps other than games and the browser that need anything above a 10yo phone to run perfectly.
For mobile games, that's a given, but it's something that only kids care about.
As for web browsing, it will forever be trash because HTML/JS is such a shit and inefficient way to access information. You could put a quantum computer in the phone and it still won't be as responsive as a native app using a fraction of the resources.
PCs became "good enough" for speed back then, but not for power consumption. There's always room for improvement there, and modern laptops really blow 2010-era laptops out of the water when you look at that metric, and also size/weight.
Major companies seem to be betting that AR eyeglasses that look like normal glasses instead of ski goggles will eventually replace smartphones.
On the data center side, the whole AI revolution has been largely driven by available compute.
We keep piling up abstraction layers that effectively cancel out any processing speed improvements, so the only way to get better performance (user perceived) now is to push for better hardware (which is increasingly prohibitively expensive to do at this point).
That's what you get when the only way people build software these days is in a browser, with JavaScript/Python/WASM and 3-layers deep Docker containers. With layers of sandboxes in-between, and countless libraries and API abstraction layers for every single little thing.
Look at how bloated apps like Teams/Zoom/Slack are - sending a fucking plaintext buffer between two computers without using at-least 1GB of RAM on each client machine is somehow an unsolved problem in 2023.
It's also incorrect to only consider phones, as TSMC manufactures many (most?) of the non-x86 laptop/desktop CPUs, where performance is much more overtly desired.
The final point is that this isn't just a matter of smaller equals faster, but also smaller equals less power - which I assume does matter to phone users.
Man, it used to be (in the Ultrabook era and before) you'd get a thin and light that's drastically underpowered, runs hot, has a terrible screen and/or keyboard, has a battery life of 3 to 5 hours, and no GPU. Even the premium laptops like the Lenovo X1 were a series of tradeoffs.
Now for a similar price, a modern MacBook is fast, silent, can play casual games or do GPU accelerated editing, has industry leading screens, and lasts all day. And they finally have HDMI ports again (heh).
In my 30 years of laptop usage (almost entirely Windows and Linux), the Apple Silicon Macs are far and away the best laptops to have ever been made. Nothing else even coming close. Things that feel slow on my 2019 i9, and cause the fan to run full blast, are multiple times faster and cause no noise at all on the M1. And this thing is more powerful than the top of the line Alienware gaming laptops from a few years ago, the things that weight like 18 lbs and another 5 for the charger. The efficiency makes a huge difference in my daily quality of life.
Maybe that doesn't matter to you, but it makes my work so much nicer. Of course, if you don't value the same things... good for you! I'm jealous, and wish I weren't such a gadget head.