RowPress: Amplifying read disturbance in modern DRAM chips [pdf]

Ultimately the complexity of managing all these DRAM corner cases needs to be handled inside the DRAM itself as there's just no way for DRAM controllers to be revised to cope with every new and exciting DRAM hardware bug. Sadly, the DRAM vendors continue to get away with publishing specs for their hardware that the hardware doesn't meet. Once upon a time that would result in a recall.

I found a Micron datasheet that specifies that (some of?) their commercial DDR5 modules are specified for operation up to 95°C, though the refresh rate must be doubled above 85°C. (https://media-www.micron.com/-/media/client/global/documents... page 13)

This matches what's in the DDR5 specification itself (https://raw.githubusercontent.com/RAMGuide/TheRamGuide-WIP-/... pdf page 320 / table 392)

Typically commercial RAM has a temp range of 0 to 85degC. In the olden days, you constrained your IO timing on the device/chip that drove the ram so that it worked at all temperatures at the rated speed. (Well, unless you were a 90s graphics card integrator...)

Now, at least since DDR3, PVT variations are continually calibrated out at runtime. So as the temp goes up, you still get periodic, quick recalibration.

DDR4 and now 5 have even more extensive compensation to keep the electrons flowing at the edges of our current ability. Did you know that GDDR5 has had the ability to CRC data bursts since 2008? Now it's come down to normal memory.