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Comment by p_l | Hacker News Reader

Before NextGen, AMD built an instruction decoder from x86 to AMD29k (which was Berkeley RISC style) and used it in K5.

Are there references about it using the actual 29k instruction set internally? Some (non primary) sources from cursory web search seems to say it used custom micro-ops which it did call "RISC ops", and had other implementation pieces carried from a abandoned 29k chip project.

There are persistent mentions of being able to switch off the decoder and use plain AMD29K instructions, but I never found any proper docs - don't have K5 to test against either.

Got interested in amd29k for about a week before finding something else to mess with. Quick attempt at ghidra support, but never really RE'd with it, so no clue how does on larger projects.

https://github.com/mumbel/ghidra_a29k

Wow, really? Cool!

The 29K was a really cool architecture and I’m sorry it didn’t make it. AMD’s pathetic marketing of the time couldn’t even beat MIPS’ terrible marketing, plus MIPS had SGI (and later SGI had MIPS).

Funnily enough, new AMD29050 are still being made (maybe even with further development) by Honeywell - they form the basis of their range of avionics computers like Flight Management Systems etc.

The 29k was a pretty rad architecture, indeed. The CPU register file had 128 local registers and more than 64 global registers as well as two program counters, to start off with. Local registers could also be accessed indirectly. At a time of the register starved mainstream x86 architecture, it felt like rolling in gold and shrieking like a little piglet in ecstasy.

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