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Comment by _hypx | Hacker News Reader

The problem with chiplets is that you can only fit so many of them in a realistic package. Once you hit that limit, you will need a way to pack more transistors on a single die. As a result, chiplets can only partial solve some of the issues of Moore's Law. It can't be a long-term extension of it.

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I suppose that the packaging problem can be solved - up to a point - with stacking vertically as well as placing them next to the io die. Wonder how well that will scale, could we stack multiple chiplets high? What effect would that have on thermals?

Vertical chip stacking is another idea being proposed. But as you said, that will have thermal problems.

It could be possible to stack less power-hungry chips like cache chips, but probably not the main CPU/GPU core. It will just be another way of extending Moore’s Law.

Would the X3D cache setup for the newer AMD CPUs count as vertical chips?

I'm a bit naive of the actual... physical bits. I'm not clear what makes a chip, and if the cache would be that - or something a bit simpler

Yes, it totally counts and is indeed being vertically stacked on Ryzen products today. Cache takes up a huge portion of total die area and doesn’t hurt temperatures too much.

For now, AMD is using the technique to add more cache to their CPUs rather than moving all of it to another layer.

As I understand it, this is because the 3d stacking is fairly expensive (it adds a lot of silicon and extra manufacturing cost), so 3d cache only makes sense once your chip is too big to put all the cache in 2D.

I suspect there is a yield issue also. that is one large chip with one defect in the wrong place is just glass. with chipsets you would assemble the module after chipset unit test.

but maybe redundancy and binning has made this moot.

What if you added tiny hollow channels between each layer of stacked chiplets and pumped coolant through them at high pressure

This is probably a dumb question but what is stopping us from just making bigger CPUs?

Wafer defects, which, among other reasons, are caused by random dust occuring between the ultraviolet lamp and the wafer (https://en.wikipedia.org/wiki/Photolithography). For some fixed concentration of dust in environment, the larger the die, the bigger the fraction of dies which have at least one defect (the lower the yield). It also depends on how robust the circuit design is to defects - defects could be detected, faulty circuit portions could be localized and then the circuit could route work around them.

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