Apple Silicon Mac Pro uses PCIe switches to support all slots

That sounds like a good description but do you think the term serial should be worked in there?

Where I get confused is what is the extra kW doing? It has been at least a decade since I did any intense projects but doesn't 15kW represent the power of an average American household circuit. The entire Mac Pro only supports 3 8k displays with built-in hardware. One would need to add SDI cards to add extra displays but the computer only draws 300 Watts. I could get 50 Mac Pros and give up which would give 150 8k displays without expansion. Maybe one gives up the convenience of a single card solution but there maybe other advantages.

I'm mostly curious as to what this work load consists of?

but when I read the number 8k encode and decode streams 15 kW represents

How much of the power is just getting the data in and out of the card to the processor. Apple Silicon doing the same work on die is going to use less power. I don't doubt that there are faster processing units.

> Because engineering effort is not free.

Obviously, but that does not explain why CPU hot swap is inherently expensive. Engineering effort is required to make any CPU.

Why must the engineering effort specifically relating to CPU hot swap inherently cause architectures that supports CPU hot swap significantly expensive compared to architectures that does not?

As a lay man without any experience with actual semi conductors outside of university, I would have thought that this would mostly be something that needs to be designed and specified once and then it could be mass produced. Clearly it will take some effort and you would have to spend some gates on it in the chip design.

Considering all the other stuff that are in modern CPUs and chipsets, I would have thought it would be possible to do rather cheaply if mass produced.

Mainframes has been doing hot-swapping everything for decades. OS and motherboard is just supposed to tolerate multiple CPU crashes. Technical feasibility of that is a long-solved problem, only economically it's dubious.

The equivalent to flushing your register state is more comparable to a context switch than a complete shut down. Also Thanks to PCIe CPU swapping could be done in pure software at the OS level. No further hardware changes required. Simply copy the contents of your RAM to the other CPU card and manage the hand-off. This is clearly different from a complete shutdown e.g. all devices on the PCIe bus would be able to keep their state.

A good programmer familiar with the target OS and inner workings of PCIe could deliver a working prototype within a week, production ready within less than a year.

None, you also need a fault-tolerant OS like Stratus VOS, but the question was not limited to Macs. I doubt they will sell many Mac Pros, the Studio’s rendered it irrelevant.

And Thunderbolt. Show me all those phones with Thunderbolt :).

the 60W envelope is the phone part

I mean you can't style yourself a workstation if the lights don't dim when turned on

All fabs have libraries that their customers use to turn chip RTL to actual transistor layout to be fabbed.

Apple silicon is made using mobile libraries, same as their iPhone and iPad chips. Even though they're made on these dense libraries, the chip is still very big, since they need to include CPUs, GPUs, NPUs, and all of their fixed function hardware.

All of this puts a limit in terms of frequency and core count. You will find that other server hardware in this price range significantly outperforms Apple silicon , save for those video workloads they're missing fixed function hardware for.

M2 Ultra has some 134B transistors, when you compare with an equivalent chip like MI300 (146B), you find that really, in terms of raw compute, there is no comparison. We will have more details on MI300 today, watch out for the news cycle.

This is an excellent read in terms of what difference using dense vs performance libraries can make - https://www.semianalysis.com/p/zen-4c-amds-response-to-hyper...

> just without consideration for constraints imposed by the phone's footprint

If you don't have those constraints it is easy to just "copy and paste" more cores and naturally this will have a higher power envelope, but in essence this is a phone tech that you pay extreme premium for.

The memory bus is overblown.

M2 Ultra has 800GB/s, which sounds like a lot until you remember a Xbox Series X has 560GB/s and costs $499. Or spend $800 and get a 7900 XT which has 800GB/s.

Think of the Ultra more of a GPU that happens to have CPU built in.

I think you are making up your own yardstick and claiming it’s universally accepted.

One instance is that PCI lanes didn't exist when the term was conjured up therefore can’t be part of inherent definition.

The mac pro has 64 lanes acroos 6 slots. PCI-e external expansion is another 8 ports of expansion limited to 40 GB/s. Unfortunately the concept of lanes doesn't seem to exist for external PCI-e ports so its hard to judge if those would count as more lanes than a normal desktop.

The 20 year old workstation is to demonstrate that the slab form factor has been called a workstation from the beginning.

For server applications, i.e. for multi-threaded applications, what matters is the aggregated throughput, i.e. the product between number of cores, IPC and clock frequency. For a given performance it does not matter if the same product value is obtained from more cores with lower IPC or fewer cores with higher IPC, and the former choice is more economical both in die area and in power consumption.

A high IPC is good for interactive applications that cannot be parallelized, so the latency between request and reply is determined by the product between IPC and clock frequency. Intel and AMD can achieve a lower latency than Apple only by raising the clock frequency, which is paid by an increase in power consumption that exceeds a lot the increase in performance.

So choosing to design a CPU with a higher IPC has contradictory effects on its efficiency for throughput-oriented (server) and for latency-oriented (personal computer) applications.

Higher IPC is relevant for workloads that are compute- but not data-intensive. There are practically no common server applications with that characteristic. In high performance computing, you might find some such applications, e.g. some Monte-Carlo-Type simulations, some linear-algebra-heavy workloads. Of course especially the latter are reported in popular benchmarks like the Top500, so marketing puts a special emphasis on those. But even there, raw IPC is mostly useless, since common problem sizes make a lot of network communication necessary to e.g. solve computational fluid dynamics problems. For those you'd need both IPC and (low latency and high bandwith) I/O, because one machine won't be enough and you have to do clustered computations with lots and lots of I/O-intensive communication to transmit your boundary results to your neighboring machines.

But run-of-the-mill server workloads are more like database applications (get query, load data from mass storage, do some processing on it, send results to network), HTTP and similar servers (get request, load data from mass storage, do some processing on it, send results to network), file servers (load/store data from network, only a little processing), terminal servers (wait for user interaction on network, process/load/store a bit, shovel out screen updates). Lots and lots of I/O, not so much computation that would care about IPC.