I thought the Anandtech coverage did a bit better job filling in both background & details. https://www.anandtech.com/show/18894/intel-details-powervia-...
One of the wild things to me is how incredibly elaborate chipmaking as become over the years. Per Wikipedia, the 6502's layout was made with "a very manual process done with color pencils and vellum paper". That's the processor that launched the personal computing revolution, powering the Apple II, Commodore PET and VIC-20, the Acorn, and the BBC Micro. Nearly 50 years later, things have gotten so fiendishly complex that "flip it over and put some stuff on the back" is a major industry change requiring who knows how many billions in R&D.
Is not a true statement.
And this sad state of affairs shows no sign of evolving favorably. Closed-source software and corporate interests at their finest.
I don’t really think chip making is much like that. I wouldn’t say that chip making was the first industry to be automated by computers either.
P.s. in case you never heard of BPD technology, https://semiengineering.com/challenges-in-backside-power-del... is also informative (thanks @rektide for the Anand link!)
Edit:
Relevant quote from TFA which somewhat answers the above question:
> Of note, because the carrier wafer is on the signal side of the chip, this means it presents another layer of material between the transistors and the cooler. Intel’s techniques to improve heat transfer take this into account, but for PC enthusiasts accustomed to transistors at the top of their chip, this is going to be a significant change.
TL;DR: No.
Intel's implementation has other factors, as discussed in the Anandtech article. Normally there's a fairly thick silicon base underneath the transistor layer, but Intel polishes that away to nearly nothing after the frontside signal wire layers are put down (to make hooking up the backside power easier). That greatly reduced structural strength & is a somewhat taxing process, so before doing the polishing down, they put a carrier wafer atop the frontside signal wire layers, adding some structural strength. And there it stays.
Which means now that the top of the chip has a carrier wafer just for structure. Then the signal wire layers. Then the transistor layer with a bunch of PowerVias also in it. Then the backside power layer.
In the first sample chip, there's still a quite a few signal layers, 14, Vs 15 on other chips. Only down by 1. But better chip utilization and other benefits (ir droop). The backside is 4 layer. Maybe maybe the backside power delivery might have (or maybe could someday) greatly let them cut down on the number of wire layers, which are all now between the transistors & the heatsink. But not yet. So there's a significant number of layers of things burying the transistors now.
None the less, the thermals here looked fine.
It's a great article.
If not, I would intuitively think this whole approach would fail?
You might want to read this: https://en.wikipedia.org/wiki/Design_for_testing
This process is automated, and for a given chip you might have a few gigabytes of stimulus total, which can collectively identify a single failed transistor (and kick that part out of the batch).
Now, I have no idea how you take a picture of a bad transistor. That's beyond me.
Or why you would want to.
Seriously? The chip is inside a carrier but enthusiasts care which side the transistors are on? Absurd.
Reading on my phone using Firefox with adblockers. Why are you using no adblockers.