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Question: do the implementation of single instructions compile to single instructions if targeting RISC-V with optimisations enabled? That would be really awesome if compilers realise what your code is doing and replace the implementations of instructions with those instructions.

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Not really, my implementation isn't smart enough to guide compilers to the right solution. Trivial instructions, like xor, are of course recognized, but for example the 32x32 mul implementation isn't. Maybe compilers will be smart enough one day...

https://godbolt.org/z/WEcTzKf7M

Yeah, well, the rock that breaks your pick in that scenario is copying all the processor state back and forth to/from the emulation model, including flag register bits, and also correctly handling exceptions and faults. Emulating the instruction’s happy path is just scratching the surface.

In the guest, you trap on reading emulation state, so that the source of truth is the hardware. Rather than use something like KVM I wonder if you could run another child process and use P trace?

> including flag register bits

RISC-V doesn't have those. Compare+branch is a single instruction.

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