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When I was in grad school programming on a Cray, "vectorization" was about chaining operations across an array and getting the inner-loop dependencies right, rather than parallel operations across elements of wide words. Interesting how the definitions have changed with architectural changes.

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From what I recall, in vector machines, operations are still done in parallel due to chaining; the difference is that you're doing e.g. add(v[1]) and mul(v[0]) in parallel, then add(v[2]) and mul(v[1]), and so on, rather than add(v[0]) and add(v[1]) in parallel, then mul(v[0]) and mul(v[1]), &c, which makes support for any vector length trivial.

(I'm sure you know this; this is just for the benefit of anyone else perusing the comment section.)

That sounds like what would be called a pipeline today.

This presentation seems very “let’s get ya going on the Xeon’s we’ve got in Stampede today” focused. Which, to be fair, is probably what lots of researchers who are interested in using (rather than studying) HPC need to know.

RISC-V has, or at least had, some classic vector extension proposal. Not sure if it actually got implemented.

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