EDIT (leaving old for reference):

The reset pin "master core release" appeared with POWER9 to support BMC-less (IBM docs lingo: SPless) boot process, and depends on tying JTAG_TMS pin high to enable autostart mode (OpenPower and FSP tie that pin low and use FSI magic write to trigger SBE)

I believe the actual "go" signal is a pin separate from FSI since POWER8. Even in the BMC-less bootstrap (documented for power9 but afaik not used by anyone) you essentially need to have a bit of logic on motherboard responsible for sequencing startup and only releasing the cpu reset pins once power is stable etc.