Cool analogy. Makes a great reference point.
As an ASIC guy, I like to occasionally casually mention to software guys that at 3GHz, light travels about four inches in one clock cycle, and it frequently really blows their minds.
As an ASIC guy, I like to occasionally casually mention to software guys that at 3GHz, light travels about four inches in one clock cycle, and it frequently really blows their minds.
180,000mi/sec * 5280 * 12 = 11404800000 / 3,000,000,000 = 3.8inches.
Extending that a little further... on a 45mm i7 chip going from one end to the other and back would be ~3.5inches of travel. Gives me an idea of how much of a constraint packaging is.
speed of light = 3 x 10^8 m/s
3 GHZ = 3 x 10^9 /s
So 3 x 10^8 / 3 x 10^9 = 0.1 metre = 10 centimetre = okay, 3.9 inches
But then metric always saves your ass. Back in physics class, they'd ask you how deep the well was if you dropped a stone & heard the water splash in 10 seconds. Before the American students could even begin their work, all the Indians would yell "500 metres!" And that's cause the gravitation constant is 10, so one half 10 times 10 times 10 is 500.
It's probably much less than that because paths in the CPU aren't straight lines. Also the i7 is a 4-core die, so it's unlikely that any signals need to go across the entire die in one clock. (Besides the clock signal, of course).
[1] http://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microproc...
Check out the animations under "Clock Distributions" (numbers 19 to 25. It shows how the propagation of the clock across the die is affected by frequency (When a part of the fabric/tree is up or down it represents 1 and 0 respectively).
My favorite is the SymTree and Non-Uniform SymTree (23 and 24) which shows how having a non uniform load at various parts of the chip and a fixed tree structure affects how long each part of the chip is at a 1 or 0 state (i.e. a low load part of the chip will spend more time at a stabilized 1 or 0, while a heavy capacitive load at one part can not even reach a true 1 or 0).