For languages like C++ and Rust the memory model is part of the language and so is taken into consideration by the compiler backend too. Code that's explicitly asking for Relaxed (the fastest ordering, which has no benefit on x86) is fairly rare.
Hmmm. Fair point. I got this argument from a HW engineer I know. You forced me to think more about what he was saying. His point was actually that the TSO model requires the HW to keep track of more stuff. More stuff uses more energy and adds latency to every memory access. It also limits how many accesses the memory subsystem can handle in parallel. He points out that ARM, RISC-V and even ia64 (Itanium) chose the relaxed model because it is better.