I think the intent here is to say that decoders' current power consumption is reasonable (i.e., within reason), but widening them could make their power consumption unreasonable (i.e., too high).
Maybe but maybe not.. the E cores on Raptorlake have two 3 wide decoders, apparently it can decode 6 instructions this way(though how often or reliably that is I don't think Intel has said).
Note that Golden Cove has a 6-wide decoder, and does not have a clear advantage over Zen 4 with a 4-wide decoder. Other parts of the architecture affect performance more, so it doesn't make sense to put more area and power budget into the decoder.