That being said, for FPGA/ASIC layout & similar problems, it's possible that QC is worth it as an extra optimization level even if slower to get a result in absolute terms to eek out that last bit of optimality (e.g. LTO equivalent). It may also be useful as a way to evaluate how good existing heuristics perform against the true optimal route to see if there's any improvements that can be made to the heuristic algorithms or the heuristics being used themselves.