Comment by TanjB | Hacker News Reader

Comment by TanjB | Hacker News Reader

DRAM is not greatly affected by radiation, because the capacitors are large structures relative to radiation events. SRAM is affected, which is why SRAM arrays should always use SECDED ECC.

The dominant cause of DRAM failures is bit flips from variable retention time (VRT), where the cell fails to hold charge long enough to meet refresh timing. These are believed to be caused by stray charge trapped in gate dielectric, a bit like an accidental NAND, and they can persist for days to months. This is why the latest generation (LPDDR4x, LP/DDR5) have single bit correction built into the DRAM chip. Along with permanent single cell failures due to aging this probably fixes more than 95% of DRAM faults.

The DRAM vendors sure could do a lot better on publishing error statistics. They are probably the least transparent critical technology used in everything, but no regulation requires them to explain and they generally refuse statistics on faults even to major customers (which is why folks like AMD run large experiments at supercomputer sites to investigate, and most clouds gather their own data).

That said, DRAM chips are pretty good. The DDR4 generation probably had better than a 1000 FIT rate per 2GB chip, so in a laptop with 16GB that would have been less than 10 error per million hours, or under 1 per 50 laptops used for a year.

For many of us the vast majority of data is in media files. I personally notice broken photos and videos every now and then. I would love to have a laptop with a competent ECC level, but they do not exist. Even desktop servers often come without. It is unclear how much better the LP/DDR5 generation will be since the on-die ECC still does not fix higher order faults in word lines and other shared structures, which may sum to as much as 10% of aging faults. All simply educated guesses, since the industry will not publish.

So this might be a dumb question but it's been bothering me and you sound like you might know.

What's the big advantage of DRAM over SRAM? In school we learned that DRAM was cheaper -- but surely the difference between 1T1C and 6T isn't more than 6 and my intuition says C is big so it's probably 2 or 3 or something for a given process generation. The problem is that the latency of DRAM is absolutely dreadful. On one hand I see a staggering amount of engineering that goes into hiding DRAM latency, and on the other hand I see that DRAM has become so cheap that many systems are over-provisioned by a factor larger than its theoretical cost advantage purely by accident. The "obvious solution" would seem to be DIMMs of SRAM with (comparatively) wicked fast timings -- but this doesn't happen, despite the fact that the memory industry is extremely competitive and filled to the gills with smart people, so presumably there's another factor that stops "DIMMs of SRAM" from being viable. Do you happen to know what it is?

Density. Storing a bit in DRAM requires one capacitor, whose dielectric is simply the gate insulation layer on a transistor. Storing a bit in SRAM takes at least two complete transistors.

That's precisely the answer I didn't find convincing for the reasons I mentioned. If it were that simple, I strongly suspect we would have SRAM-DIMMs and DRAM-DIMMs duking it out in the marketplace in analogy to SSD vs HDD a decade ago.

> one capacitor, whose dielectric is simply the gate insulation

Every DRAM cell depiction I've seen in the last ~5 years has had a gigantic trench capacitor. Are those not in production?

Density isn't the only issue - power usage is also a contributing factor. Because SRAM uses more transistors per bit, leakage of the transistors in large arrays is a significant source of power draw. In DRAM leakage of the single transistor per cell can be compensated for by adjusting the refresh rate.

MRAM and other persistent memory technologies might be used someday, but there's a lot of R&D work to get them to the same level of price and performance as DRAM. It's sad that Intel gave up prematurely (imho) on Optane.

and it's not like SRAM isn't used in modern computers -- it's baked directly into the silicon of your CPU to serve as register banks and cache

Ah, that makes sense! It's too bad that CMOS becomes leaky at small sizes.

Yeah, too bad about Optane, but CXL gives me hope that the next decade will bring more action in this space.

Great question! I wasn't smart enough to ask it myself. Gonna learn something here I hope. ..

>SRAM is affected, which is why SRAM arrays should always use SECDED ECC.

How many SRAM arrays exist in electronics we use every day that don't have, at minimum an error detection and reset mechanism? What about hardware registers that aren't structured as 2D arrays, how often are those protected? Things like buses and counters are at least somewhat vulnerable too.

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