Why do they sometimes include other signals than clock and asynchronous reset/set in sequential process sensitivity lists? For example D in Listing 6.2. The extra signals in the sensitivity list don't add any functionality, and might be confusing to the reader.

It's probably good to teach the two process FSM first, because it resembles the mathematical model, but back when I did VHDL design, I found single process FSMs more straightforward. Can't remember what they looked like exactly, but something like Thompson's answer here: http://stackoverflow.com/questions/5961751/encoding-state-ma...