Apple uses LPDDR4 modules soldered to a PCB, sourced from the same Korean company that everyone else uses. Intel has used the exact same architecture since Cannon Lake, in 2018.
> Apple uses LPDDR4 modules soldered to a PCB, sourced from the same Korean company that everyone else uses.
Apple might have sourced and soldered on LPDDR modules from the same company, but it is not LPDDR4 and it is LPDDR5 6400 connected via a 256 (Pro), 512 (Max) or 1024 (Ultra) bit wide memory bus.
> Intel has used the exact same architecture since Cannon Lake, in 2018.
Other than LPDDR5 6400 had not existed in 2018, no Intel CPU has ever used a 512, leave alone 1024, bit wide memory bus even in the server setup. Wide memory bus is conducive of faster concurrent complex builds, and Rust / Haskell builds show significantly faster build speeds as well.
> Rust, cargo build for our "test world binary".: 64 core Threadripper 3990x @ PBO level 3, ~400w, with Optane drive - 1 min 37s M1 Max, 64 GB, on battery @ 30% charge - 1:34s
What is somewhat relevant as the source of confusion here is that Apple puts the DRAM on the same package as the processor rather than on the motherboard nearby like is almost always done for x86 systems that use LPDDR. (But there's at least one upcoming Intel system that's been announced as putting the processor and LPDDR on a shared module that is itself then soldered to the motherboard.) That packaging detail probably doesn't matter much for the entry-level Apple chips that use the same memory bus width as x86 processors, but may be more important for the high-end parts with GPU-like wide memory busses.
Last I checked apple M1 max chips have up to 800GB/s throughput, whilst AMDs high end chips taper out at around ~250GB/s or so, closer to what a standard M2 chip does (not max, or pro version). at the top end they've got at least 2x the memory bandwidth than other CPU vendors, and that's likely the case further down too.
(The M1 Ultra is the one with 800GB/sec bandwidth on paper)
Where it gets interesting is how access to the memory is multiplexed in the most extreme case where 3x CPU clusters, 32x GPU and 16x ANE cores are attempting to fetch memory blocks at different locations and at once. It is not unreasonable to presuppose that Apple Silicon contraptions use the switched memory architecture, however with such a high degree of parallelism it is very intriguing to know how the memory architecture has been actually designed and optimised. High performant memory access has always been a big deal that usually comes with big money attached to it via a, naturally, non-memory bus associated connection.