Comment by user070223 | Hacker News Reader

Comment by user070223 | Hacker News Reader

From my understanding

FPGA doesn't have the instruction pipeline as the command is encoded in the gates themselves. It means that on runtime the FPGA is not turing complete[0] as opposed to the CPU[1].

There is a phrase "data is code and code is data" in security context. The new saying if FPGA would ever replace cpus' as the main computation hardware(as you don't need turing complete when you keep using the same apps[microservices]) is something like "code is execution and execution is code" as you imprint the code in the gates. It would get rid of a whole class/subclass of memory safety vulernabilitie.

This paradigm change is like what webassembly did to the web. The slogan should be "make the bitstream go mainstream" Some made a demo running wasm on fpga[1], not sure if using a cpu or directly

of course you move complexity to compiling, and increase loading speed, all for order of magnitude faster execution

Companies devloped high level synthesis compilers but it's diffcult and challenging as you need to synchronize parallel excution piplines which you don't have to in cpu since it has steady clock rate for each step in the pipeline

A copmany named legup computing(acquired by microchip) compiled memcached/redis applications to fpga and improved perfromance & power efficency by an order of magnitude(10x)

There are a lot of intellectual properties in hardware design as opposed to software so tools and knowledge is scarce.

If anyone works / want to work on this problem hit me up in the comments

[0] Unless you implement a cpu on top of the fpga :)

[1] Assuming infinte memory, which is false, but good enough

[2] https://github.com/denisvasilik/wasm-fpga

I've had this idea for a while: make an FPGA capable of executing WASM bytecode, then offloading WASM execution to the FPGA. Sounds like a fun project to learn FPGA and how to make a CPU.

Sorta off topic, but I wonder if a CPU with WASM bytecode as its native instruction set could be more performant / power-efficient than JIT-ing WASM code to ARM/x86 assembly. My understanding is that modern processors comes with a wide range of optimization tricks like register renaming, out-of-order, superscalar, ... such that it's probably just easier to JIT WASM bytecode to the native instruction set, so we'd get those optimizations for free, as opposed to design your own WASM CPU with those same optimizations.

> FPGA doesn't have the instruction pipeline as the command is encoded in the gates themselves. It means that on runtime the FPGA is not turing complete[0] as opposed to the CPU[1].

That obviously depends entirely on the circuit, many sufficiently advanced circuits probably end up being accidentally turing complete.

You can implement turing-complete CPUs in FPGA fabric.

That's exactly what OP's footnotes say, yes.

there's a hint that you are misunderstanding how things work a bit here. By the time you get to the footnote: "Unless you implement a CPU on top of the FPGA :)" you realize that of course FPGAs can be turing complete, but it's not really correct to say "on top of", more correct with be to say "implement a CPU with the FPGA. Secondly, you never say a CPU isn't really turing complete (footnote: unless you use JMP instructions). We would typically class machines class using the maximum possible because it's usually trivial, but uninteresting, to, for example, program or limit a Turing machine to not be Turing-complete.

Your other footnote is spot-on. I refuse to consider CPUs to be Turing complete (out of pedanticism) because given physical memory constraints. Realizable physical computers are, like all digital logic circuits) actually Finite State Machines with just really, really big state space (like 2^(~10^15) states). If you put every single flip-flop and DRAM bit back the way it was and execute the next clock, it will deterministically follow the same pattern. They aren't even PDAs (Push-Down-Automatons). EVERYTHING is an FSM (pedantically). Turing machines and PDAs are theoretically useful models for theoretical computer science and math, however. But not technically accurate.

FPGA's aren't CPUs that lack instruction pipelines. They are universal ASICs and/or digital circuits that are re-programmable. ANYTHING that can be accomplished with synchronous (clocked) digital logic circuit can be implemented with an FPGA, including CPUs, but also potentially many, many, other things.

> [0] Unless you implement a cpu on top of the fpga :)

You should revisit what "Turing complete" means. The whole idea is based on one architecture being able to perform the computations an other architecture can by implementing a sort of emulator of the other architecture.

So the fact that the FPGA can implement a CPU shows that the FPGA is Turing complete, there is no "unless" about it.

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