Implicit assumption that the Pi's PCIe doesn't follow the spec? There is a lot of room between "it works in our target market" and "it follows the spec". I only mention that because I have come across a number of situations where the specifications related to "downsizing" the interface when insufficient resources are detected are often ignored when the target platform is invested in providing only the maximum amount of resources. Think USB2.0 high speed devices failing to down throttle in a USB 1.1 port and still work as an example.

That said, there are often latent bugs in these situations that this sort of research/experimentation can uncover. Manufacturers would do well to invest the time in understanding why it doesn't work because those reasons can often lead to problems that are hard to catch when it is working.