The basics of decoupling capacitors
lcamtuf.substack.com
lcamtuf.substack.com
A lot of design guidelines and advice boil down to cargo-cult rules like "sprinkle 100 nF caps everywhere," and many people don't have don't have the tools to measure PDNs and decide if that rule is actually good enough.
I made a custom PCB to emulate different configurations of capacitors of various types and layouts. With a spectrum analyzer and tracking generator, it's possible to measure and visualize several points that are important: what does "physically close" mean, the effect of DC bias on capacitors, and how does parallelizing capacitors together affect the circuit. The author of this is using an oscilloscope to look at time domain behavior, but generally I think of these things in the frequency domain.
I only know two commercial VNAs in-production that are made specifically for this kind of work: the Keysight E5061B (5 Hz - 3 GHz, $50000+ when optioned out appropriately) and the Omicron Bode 100 (1 Hz - 50 MHz, I think $5k-10k).
The FRAs span the same price range as the VNAs you listed. Having a low-cost version of each can extend the frequency range over which you can make good measurements compared to just one tool of similar total price.
The Bode 100 sacrifices some low and high frequency range and performance to be a 2-in-1.
VNAs have become remarkably cheap; here's one that < $ 60 https://www.amazon.com/50KHz-900MHz-Analyzer-Measuring-Param... I have one of these, it works very well.
Fancier ones are of course available. This one goes to 6.3 GHz https://www.amazon.com/LiteVNA-64-Analyzer-50KHz-6-3GHz-Port... and is $ 180.
I have this 'fancy' one: https://www.tindie.com/products/hcxqsgroup/nanorfe-vna6000/
One trick I learned from the RF guys is: put two same value capacitors in parallel; it doubles the capacitance, and also reduces by about half the ESL (inductors in parallel rule). Clever.
As /u/exmadscientist mentions, you probably shouldn't do this unless you know what you are doing.
I also want to mention here that the fancier MCUs and SoCs will have configuration registers for drive strength, slew rate control and more for each output pin. If you're having a problem with ringing or whatever, you should definitely look to these settings, and see if you can fix this way. You might not need to make a PCB design change, which is always nice.
You don't do this kind of thing with ferrite beads unless you need genuine high frequency isolation--generally because you are using a high precision ADC/DAC. A small resistor is more than good enough to round this off on an I/O pad.
I always put a small (47 Ohm, 33 Ohm, or 22 Ohm) resistor in series with any digital "clock" line nowadays (SPI-SCLK, I2C--SCL, etc.). Modern chip processes can launch edges with GHz components onto clocks that are operating at KHz. I have had to debug quite a few "double clocking" faults and invariably just putting a small series resistor does a nice job of completely avoiding the problem.
https://www.allaboutcircuits.com/technical-articles/x7r-x5r-...
In my experience, 0402s are the breakpoint on the curve.
0603s are large enough that there are a couple of cases where they're kinda marginal due to size (inductance) and the size gain isn't quite enough for things like QFN packages. 0402s almost never have the issue. 0201s aren't enough better that they are worth the extra grief to deal with unless I'm on a really constrained board, and I'm only letting an assembler do the board (nothing by hand from me).
Here's a shortish video I found useful on this: https://www.youtube.com/watch?v=k7aPb585Y6k&t=189s
Correct solution for this issue is debouncing logic (be it in HW or SW). But if for your application an SPDT switch costs same as SPST switch, driving an RS flipflop from that works better (less latency) and component-wise is cheaper than deboucing in HW (same amount of logic, less passives).
A capacitor resists change in voltage. Where a switch's change on the oscilloscope usually looks like a steep cliff, adding a capacitor will introduce a curve as the voltage drops. The size of the curve depends on both the capacitance _and_ the resistance between ground and the capacitor: simply adding a capacitor won't give you much of a curve because there'll be very little resistance. You also need to add a resistor to make an RC network.
To handle the worst of switches you want an RC value somewhere around 10ms. What you choose for R and C depends on any other constraints you might have, like power consumption or capacitor size.
Because the RC network slows the transition time a lot you need a Schmitt trigger to convert the slowly curving voltage change into a nice sharp input signal change without allowing noise to ruin everything.
There are other ways to deal with bounces in hardware, too: you can convert the switch's on/off signal into a pulse using a monostable circuit (eg, a 555), you can use a dedicated debounce IC, you can use a flip flop with a SPDT switch, you could blow $50 on a Hall effect switch and use an ADC.
Or you can deal with it in software, which is popular because it's typically easier to find space in a ROM than it is to find space for discrete components on a PCB.
> A related trick is to put ferrite beads on MCU output lines
You must be extremely, extremely careful with this. In general, ferrite beads are hard to apply correctly and great care is required if you want them to work out. Do it wrong and you'll probably be making things worse, instead of helping. See for example:
https://incompliancemag.com/article/ferrites-to-kill-ringing...
https://incompliancemag.com/article/all-ferrite-beads-are-no...
>The datasheets ... The manufacturer is
Honestly, the datasheets are usually just wrong. The writer is an intern and the material is cargo-cult copy-pasted. If it works it's by accident, or because it wasn't critical in the first place. Read the datasheet, understand what it's trying to do, then go ahead and achieve that end in the most sensible manner.
> It is true that at very high frequencies — hundreds of megahertz — the capacitor’s residual inductance becomes a limiting factor. At that point, combining multiple different capacitors can offer somewhat better wideband noise suppression.
Nope. It's still wrong and dumb to do this with MLCCs unless you have simulated the hell out of the whole thing. You should practically never parallel different values of MLCC. Instead follow EMC wizard Henry Ott's advice: pick the smallest package you're willing to deal with, then the largest capacitor you're willing to pay for in that package, and just use that everywhere. This is called "big V" decoupling by Ott and decoupling master Bruce Archambeault and it is not the best way to do things, but every better way is much, much, much harder to do. "Big V" will work for everything that doesn't involve underfilled BGAs, and even most of those.
> tantalum polymer
I actually kind of hate these guys, I don't find much use for them outside DC-DC converter output capacitors. They have too little ESR to damp things that need it, too much ESL for high frequency use, and are just too expensive for general use. They're not bad or anything, they just don't really have a sweet spot. MLCCs plus a few cheap high-ESR aluminum electrolytics (often found these days as the high-temp long-life parts) is a really effective combination. Maybe a few solid tantalums for intermediate bypass if appropriate.
> Y5V
Thank the heavens that these are basically extinct. Good riddance.
Okay, enough comments, you might then ask, how the hell do I decouple things in production designs?
First, put one bulk capacitor, minimum, on every rail. Aluminum electrolytic if the rail leaves the board ever, maybe tantalum if it doesn't (or maybe not, solid tantalums have... reputations). My go-to series is Rubycon YXM or YXJ for through-hole electrolytics, Nichicon UCB/UCW or Chemi-Con MLE/MLF for surface-mount, and AVX TAJ for tantalums. These can physically be located anywhere.
Then sprinkle down one 1uF 0402 per part for the small parts, or one per power pin for the big digital chips. Place these at the power pins, no exceptions. Things like MCU analog rails usually don't need ferrites but might get pi filter type structures. It depends on how important they are, really. If it's a big or dense board, toss in another tantalum or two physically near the chips or chip clusters to help keep the electrolytics honest.
You can decouple 500MHz processors and pass radiated EMC at Class B with this approach. It's not hard to do, it's cheap (but not cheapest, this isn't going to get you to Shenzhen-special COGS), and it works great.
I assume this refers to the shape of the impedance plot? I mean sure you are going to try to get the deepest, widest "V" you can but it's a game where you must optimize the cost, usually.
My favorite newish technology for this is the "reverse" footprint surface-mount capacitors, where "reverse" means the leads are on the long side of the package where they should have been in the first place, instead of the normal style where the leads are small and far apart. E.g. a backwards 0612 package has ~10x less impedance at 1GHz than a 1206. But the price is 2-3x.
The wide parts are great. But they're also overkill. You can clean your kitchen sink with a pressure washer, but why would you? You don't need to. And so you don't need 0306s for normal designs.
> I actually kind of hate these guys, I don't find much use for them outside DC-DC converter output capacitors
Bulk capacitance in extreme battery constrained scenarios?
MLCC has difficulty going above 1uF at reasonable costs... especially when you consider voltage derating. Aluminum is relatively leaky, IIRC like 20uA, or 20x more leakage than MLCC or Tanalums.
Think like bulk capacitance for a CR2032-cell (which has issues serving more than 10mA). Serving an ESP32's 100mA+ current draw for a second or two (and then ESP32 sleeps) kinda thing.
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But not really a "decoupling cap" in this case. Just a bulk cap where Aluminum is disqualified.
They do leak pretty badly though. I think it's better than other electrolytics, but it's still not great. Of course, they do tend to do better than spec... until they don't. It's been a while since I've done micropower stuff though, so what do I know.
To summarise your point about decoupling capacitors. Use physically smallest capacitor you can, but with the largest capacitance (limited by the knee in capacitor price). High frequency response is dominated by parasitics, but you will get lower impedance for the vast majority of the frequency range until you hit the SRF. A lower capacitance will be better high frequency around the SRF, but worse at every other frequency.
Don’t place ferrites down blindly. Ferrites vary wildly, impedance at 100Mhz more or less a useless specification. You need impedance graphs, and you really need to know when a ferrite lossy and not simply inductive, and when it loses effectiveness and becomes a capacitor.
If you are going to put them down blindly use the exact same part number and manufacturer as on the development board.
If you think you might need a ferrite, put a zero ohm down and measure later. Sprinkling ferrites blindly without a spectrum analyser is at best a placebo, doing it incorrectly is almost always worse than not doing it. Examples of what not to do, splitting a plane to add a ferrite, adding impedance to power pins, adding inductance to IO lines or filter network and creating resonance.
As an addendum: Power delivery network, power plane stack up, and component placement matter far the than the precise value of decoupling capacitors. Thinking in terms of current loop area is vital. The PCB is a decoupling component, and the power planes may be your only decoupling at frequencies higher than your capacitors SRF.
I prefer just to avoid that headache, but I'm just a hobbyist so...
Experiments show that solid tantalum capacitors can tolerate discharge currents at much higher levels of voltage (typically, close to the scintillation breakdown) than the charge currents, so current spikes are much more “dangerous” in combination with the increasing voltage that happens during charging. This indicates that a fast voltage increase to sufficiently high level is critical for surge current failures, and high current spikes are byproducts of the fast voltage increase rather than the prime cause of failure.
[1]: https://nepp.nasa.gov/files/24745/2013_n240_Teverovsky_ESTEC...
Can you then say why paralleling capacitors to cover higher frequency range is repeated often in literature? Was it true before MLCC? Why is it not valid with MLCC?
How does this work for something like an FPGA ? Generally there will be several power rails (Vdd, Vio, Vpll, maybe Vusb, others) in an area far too tiny to put even 0102's let alone 0204's. Or maybe I'm just rubbish at placement :)
I've been using double-sided placement underneath the FPGA as far as I can, but that also restricts the egress of the signals when you have as many power pins as an FPGA has...
Any hints for power-pin-dense applications ? Enquiring minds want to know :)
Blind and buried vias open up a whole world of space if you're willing to spend for them.
You may just need to add more layers.
I try to keep my BGAs limited to 256 pins if I can, but sometimes it will go higher - I'm looking at using an I.MXRT1176 for example, and that's 289 balls at 0.8mm pitch. I've also used Efinix FPGAs at 0.8mm pitch/256 balls. I've gone as low as 0.65mm pitch, but that is pushing the limits of where I want to be...
It's fairly common to see 3.5mil as space/trace minimums nowadays (again in the cheap(er) Chinese PCB houses). That's still not quite enough to escape two traces between each outer ball on a 0.8mm grid - though reducing the solder pad and ignoring the warnings from the board-house has worked before :)
I've never done blind/buried vias, they always seem to be a lot more expensive than the 6- or 8-layer boards I can get done for cheap at nextpcb or jlpcb. Maybe I ought to ask again...
Things like FPGAs, DDR/HyperRAM ram, etc. used to be outside the province of hobbyists, but given the packaging for those high-frequency-capable pins, BGAs are ever-more common, and with them come the layout issues.
Anecdote: I've routed a 900 pin 30x30 P=1mm/B=0.6mm FPGA with no issue on this.
Use board-to-board connectors if needed to add more "layers." P=0.65mm is definitely going to make differential pairs difficult if not impossible at this trace width.
I haven't stumbled across outright wrong just yet, but I have seen plenty of "wildly inconsistent" between layers of app notes and data sheets, especially on little RF chips. My advice to my team has been to choose the approach with the most places for caps and we'll fix it if we have to. Extra points to place caps don't hurt except when they do, and we haven't had to fiddle so far - we probably fall into "not that critical", because I'm not that lucky.
> Instead follow EMC wizard Henry Ott's advice
OK, we are on the same page. I still get schooled now and then, and Ott's treatment of this subject (pp. 444 - 447) got a post-it this decade sometime.
> It's still wrong and dumb to do this with MLCCs unless you have simulated the hell out of the whole thing.
What do you do for simulation? I haven't. I would throw a linear simulator at the problem but maybe that's just the hammer I have.
As for datasheets, they're rarely outright wrong. More... detached from reality. For example, a lot of SMPS datasheets will suggest some strange stuff. When you realize the actual rule of "place a low-ESL=physically small part right next to the regulator then the rest of the capacitors nearby", the weirdo advice starts to make sense, and you can tell what you really ought to do. That's why it's really important to separate the intent of the datasheet from the suggested implementation. The intent is usually worth paying attention to... the random use of 0.1uF capacitors, not so much.