This does not seem to be correct. Modules with an 128-bit data bus would obviously require a lot more pins. Instead what this actually seems to be about is placing a buffer between the two ranks (essentially two completely independent modules) and the data bus (presumably it buffers the command bus as well). The "128 bit" data bus on the host side is achieved by running QDR over the 64 bit wide bus.
Basically an evolution of LRDIMMs with a pinch of FBDIMM.