Tiny Tapeout: From idea to chip design in minutes! | Hacker News Reader

Tiny Tapeout: From idea to chip design in minutes!

tinytapeout.com

158 pointsrbanffy20 comments

TL;DR (i didn't do a deep dive, just a skim) they've laid out a chip into a grid of small areas and you can submit a design for one of the areas. Then they make a chip that has everybody's designs on them, so when you get your chip it has your design, and everybody else's that you can play with. The areas each have room for about 400 gates in which people have built stuff like a 4 bit CPU. An area in one corner is the "master scheduler", it multiplexes and delivers 8 bit input sequentially to each area, and gathers 8 bit outputs from each area, at the rate of about 15khz.

using all their tools and documentation to create your design is free, at a certain point when it gets to committing they have a pricing scheme which is intended to be affordable.

(note: they've been doing versions of this, the last one was tape out 2, now is tape out 3, and I was not careful about checking which version specs I was skimming so perhaps the new one is more capacious or the last one less.)

from https://hackaday.com/2023/02/14/supercon-2022-matt-venns-tin...

personally, I think it would be just a bit cooler to have a dual channel 40kHz system that could do DSP on high quality audio, but you can do plenty with this

I was excited until I saw how you interface with your "corner".

It's so slow. It's a shame, I wonder if there could be some other way?

actually, combining what i said with what you said got me to a new idea: if the different areas on the chip were sharing inputs and possibly outputs, even with the same bandwidth tech, it would be much higher bandwidth as a group.

So, for example, have a whole tape-out project devoted to something like a modular music-sampler/synthesizer. So, there's D/A A/D of a few audio/midi streams coming in, which every area of the chip gets as a feed, but also areas can talk to their neighbors directly without multiplexing, and then mixers, filters and group output. Maybe some way to "roll your own multiplexer" so somebody could use the whole chip for a variety of guitar pedals, somebody else a vocal processor, etc.

Yes. This needs to be done!

I submitted 2 CPUs to TT2 and a PDP8 (12 bits) to the current TT3.

The major limitations are the relatively small number of gates, and the external interface (8 inputs including clock/reset, and 8 outputs) - and the external multiplexor which essentially limits clock frequencies to tens of kilohertz.

TT4 and later will have a redesigned pin interface and likely have roughly twice as many external pins and far faster clocks - a lot of my designs are gates spent talking over that tiny interface

I'll also note that all Tiny Tapeout projects are hosted on github and you can browse through them if you want to see how they're done

and the external interface (8 inputs including clock/reset, and 8 outputs)

That's around the same amount of I/O as an Intel 4004.

> and a PDP8 (12 bits)

Interested. Is this going to be something like the Intersil 6120?

Probably a bit smaller - and doesn't have a multiplier/divider (it does have the minimal MQ register instructions), and it has a minimal IO interface

In some sense it's a toy because the TT internal clock is so slow and it needs to run 5 clocks/memory cycle because of the tiny bus interface - ideally in say TT 4 with ~16 bits each way in the IO bus we could actually make something that could outperform an original PDP8

You can find it here: https://github.com/MoonbaseOtago/tt03-pdp8/blob/main/src/cpu...

Why do they use large slow shift register for I/O? Cannot it be done the other way, for example: use parallel inputs and supply them to all designs simultaneously, and use large 250x1 multiplexer to read outputs?

Also one can reuse that shift register as 250 bytes of sequential access memory, although I guess this technology which has been used in Soviet calculators has been long forgotten.

I don't know the original reason for choosing the shift register, might have been that it involved lots of short wires between flops so the timing is easier to get right - but essentially they will switching to the big mux/etc next time around

I wish it was possible to do this without the crowd sourcing, I have a low-volume HDL project of just ~40 gates and 32 shift registers (+4*32 gates) which discrete is quite bulky, FPGAs are overkill and CPLD works but are often too small or unavailable.

Based on rumors maybe atomicsemi will provide this at some point.

The smallest Lattice iCE40 are under $2 in volume, it may be "overkill" but also pretty tough to beat economically at low quantities. Especially keeping in mind one of the limitations of these MPW silicon runs is the parts you get are untested... reasonable in prototyping but an obstacle to scaling up to low volume production.

Dialog (nee Silego) Greenpak is a cheaper programmable option if you can find one that your design fits in. The design flow is a little more idiosyncratic.

Of course often the cheapest option these days for low-end digital logic requirements is to emulate your logic in a microcontroller, if you can get away with that speed wise. It might not feel very elegant but the economy of scale is tough to beat.

Personally it's analog and mixed signal design that I'd love to see cheap and easy custom silicon for... I've got a design with some DACs, analog switches, jellybean op amps, and a dozen-ish discrete transistors that would be really great to integrate and miniaturize, but it doesn't seem practical at ~10k volumes.

The transistors are the hard part to integrate here. From the manufacturing side, why waste the die space on your MCU production line when you can use a much older process to build transistors for pennies.

For mixed signal design in general, the Cypress PSoC 4 series is pretty good.

Renesas is also doing a lot of work in the low BOM cost configurable analog/digital space, with Greenpak and ForgeFPGA: https://www.renesas.com/tw/en/products/programmable-mixed-si... https://www.renesas.com/tw/en/products/programmable-mixed-si...

I did consider iCE40 (mainly due to the icestorm/yosys project) for our project at the time but they weren't available I believe, I will have to look into it again. Unfortunately a microcontroller was not really an option as the ones we generally use don't have a input FIFO buffer/peripheral fast enough (clocked 25Mbit/s) although there may be others that can, we didn't look further in to it as it seemed like a pretty expensive option given the simplicity of the circuit and the HDL that was already finished.

Raspberry Pi has microcontroller that may work for you (RP2040) it has programmable IO thingy that is quite impressive). Anyway regarding small FPGAs/CPLDs - i am passively keeping eye on small/inexpensive parts - and as far as I know it is not field abound with options (Cypress PSOC, LAttice iCE40, small CPLD from Altera(Intel)/Xilinx(AMD)). Just learned about GreenPAK (Dialog and now Renesas) and I am quite thrilled. Do not know how it could fly under my radar.

> The smallest Lattice iCE40 are under $2 in volume,

Those have got open-source tools, right? And they're relatively easy to work with, I guess.

What can you do with them? Like, how "big" a thing could I make? I've got a project for which I need a bunch of programmable 16-bit counters that'll pulse an output when they roll over zero. Could I make those in an iCE40? How many would fit?

"up to 7680 programmable logic cells", so at a very conservative estimate of one cell per bit of counter that's 480 counters. So you'll probably run out of I/O first.

With all this GPT hype, it's good to see some good old fashioned hardware making the top page of HN.

it's a shame that this is limited to digital, and impractically slow digital at that

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