This conversation goes into the details about making all of this work. Along the way, we hit on pushing a cycle-accurate simulator to its limits; developing a new P4 compiler that has a Rust target; using that compiler to then develop an accurate hardware-virtualized model of the ASIC; developing a new routing protocol (delay driven multipathing); and how all of this adds to up solving some gnarly problems like microcongestion and flexible topology construction.
[0] https://share.transistor.fm/s/c80a79d8
[1] https://share.transistor.fm/s/65a10522
[2] https://p4.org/