AMD Zen2 ymm registers rolling back
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Seems to be a known errata which was fixed by a microcode update
The XSAVES instruction may fail to save XMM registers to the provided state save area if all of the following are true:
• All XMM registers were restored to the initialization value by the most recent XRSTORS instruction because the XSTATE_BV[SSE] bit was clear.
• The state save area for the XMM registers does not contain the initialization state.
• The value in the XMM registers match the initialization value when the XSAVES instruction is executed.
• The MXCSR register has been modified to a value different from the initialization value since the most recent XRSTORS instruction.
Apparently some Ryzen models have no fixed microcode available. You can boot with clearcpuid=xsaves as a workaround, probably at some performance cost.
i.e. thats what this repo seems to be: https://github.com/platomav/CPUMicrocodes
However, for some unexplainable reason AMD doesn't tend to update the microcodes in that repo particularly often, leaving it up to BIOS vendors and users updating their BIOS.
I think most people rely on the operating system to (amazingly) hot patch it during boot. Intel and AMD both publish them and are integrated regularly into most distros (and the linux-firmware git tree). Surprising/weird that they haven't released the Renoir ones.
Also seems Tavis had a bug where Debian wasn't applying them on boot for one reason but didn't give details. Wonder what it was.
But otherwise all the major consumer / gaming motherboards pick up new AGESA updates quickly & consistently, even when they're EOL platforms.
I can’t confirm that. My current board is the MSI X570-A PRO. First BIOS was 2019-06-20, the latest 2022-08-19. And that’s still updating versions and settings. After 3 years, and I’m expecting more. This has also been my experience with other boards. MB updates tend to last several years.
In my mind a CPU instruction is hardwired on the chip, and it blows my mind that we keep finding workarounds to already released hardware.
Maybe someone could dumb that down for me?
You can change the mapping from x86_64 instruction to sequence of micro-operations during boot on modern CPUs. That's what we mean by updating the microcode.
At least that's my understanding, as someone who has implemented a few toy CPUs in digital logic simulation tools and has consumed a bunch of material on the topic as hobbyist but have no actual knowledge of the particulars of how AMD and Intel does stuff.
vfmadd231ps ymm3, ymm1, YMMWORD PTR [rax-256]
Most AMD64 instructions decode into a single micro-op. Moreover, there’s a thing called “macro-ops fusion”, when two AMD64 instructions are fused into a single micro-op. For example, scalar comparison + conditional jump instructions are typically fused when decoding.
But we can agree that the complexity ceiling is much higher on macro-ops than micro-ops, right? The µop you mentioned does one (vector) FMA operation on two (vector) registers and stores the result to RAM. While in x86, we have things like the rep instruction which repeats an action until ECX is zero, or the ENTER and LEAVE instructions to set up and tear down a stack frame. Those are undoubtedly implemented in terms of lots of micro-ops.
Other examples are crc32, sha1rnds4, aesdec, aeskeygenassist - the math they do is rather complicated, yet on modern CPUs they are single micro-op each.
> one (vector) FMA operation on two (vector) registers and stores the result to RAM.
It loads from there.
> Those are undoubtedly implemented in terms of lots of micro-ops.
Indeed, but I don't think it's complexity. I think they use microcode for 2 things: instructions which load or store more than 1 value (a value is up to 32 bytes on AVX, 64 bytes on AVX512 processors), or rarely used instructions.
Almost like a CPU has an JIT emulator for x86.
It's more like an intepreter for x86, seeing as it is actually executed on a dataflow architecture.
Not sure what the distinction is but that's where it is to my mind
Compared to 'JVM JIT' or 'LuaJIT': there is no instrumentation to detect what is hot or not. The CPU frontend will crack x86 instructions into micro-ops, while looking for some patterns to merge certain instructions or uops into larger micro-ops. The micro-coded instructions (like many of the legacy instructions) are likely just lookups.
Most of this is my speculation, mind. Modern CPU frontends are still kind of a black magic box to me, but I think they are limited by relatively simple transformations by virtue of being on the critical execution path.
[0] - https://chipsandcheese.com/2022/11/05/amds-zen-4-part-1-fron...
It's not a magic arc profiling optimization either.
That part is driven via microcode (kind of like firmware) and fixes in that can fix some CPU bugs.
Which also means that one core can essentially run multiple assembler instructions in parallel (say fetch memory at same time floating point operation is running, at the same time some other integer operation is running etc.) and it just makes it look like it was done serially.
8-bit CPU control logic https://youtu.be/dXdoim96v5A
8-bit CPU reprogramming microcode https://youtu.be/JUVt_KYAp-I
In short, the microcode instructions are a bunch of flags that enable different parts of the processor during that clock cycle (eg is data being loaded off the bus into a register? Is the adder active? Etc), so to implement an instruction that says add value from memory a to value from memory b and store in memory c, the microcode might be: copy memory a onto bus, store bus to register, copy memory b to bus, store b to register, add both register and put result online bus, store value on bus to memory c. (In a hypothetical simple cpu like the one Ben built, a real one is obviously much more sophisticated). So in Ben’s toy CPU, the instructions are just indices nto an EEPROM that stored the control logic but pattern “microcode” for each instruction, and IIRC each instruction takes however many cycles the longest instruction requires (in real life that would be optimised of course).
This is also how some processors like the 6502 have “undocumented” instructions: they’re just bit patterns enabling parts of the processor that weren’t planned or intended.
So you can see that it may be possible to fix a bug in instructions by changing the control logic in this way, even though the actual units being controlled are hard wired. I guess it very much depends on what the bug is. Of course I only know how Ben’s microcode works and not how an advanced processor like the one in question does it, but I imagine the general theme is similar.
The thing is, the microcode is often using instructions that are a very different "shape" from sensible machine-code instructions, because quite often they have to drive gates within the chip directly and not all combinations might make sense. So you might have an instruction that breaks down as "load register A into the ALU A port, load register X in the the ALU B port, carry out an ADD and be ready to latch the result into X but don't actually latch it for another clock cycle in case we're waiting for carry to stabilise", much of which you simply don't want to care about. The instructions might be many many bits long, with a lot of those bits "irrelevant" for a particular task.
The 6502 CPU was a directly-wired CPU where everything was decoded from the current opcode. It doesn't really have "microcode" but it does have a state machine that'll carry out instructions in phases across a few clocks. It does actually have a lot of "undefined" instructions, which are where the opcode decodes into something nonsensical like "load X and Y at the same time into the ALU" which returns something unpredictable.
Take a simple example: the registers are made up of latches that hold onto values and have a set of transistors that switch their latches to connect to the BUS lines or disconnect from them, along with a line that makes them emit their latched value or take a new value to latch. This forms a simple read/write primitive.
If the microcode wants to move the result of an ADD out of the ALU into register R1 then it will assert the relevant control lines:
1. The ALU's hidden SUM register WRITE high which connects the output of its latches to the lines of the bus. For a 64-bit chip there would be 64 lines, one per bit. Each bit line will then go high or low to match the contents of SUM.
2. It will also set R1's READ line high, meaning the transistors that connect R1's bit latch inputs to the bus lines will switch ON, allowing the voltages on each bus line to force R1's latch input lines high or low (for 1 or 0).
Sometimes, CPU vendors run out of space for such bug fixes. They have to re-introduce another bug to free up space to fix a more serious one. That one kinda blew my mind.
fp registers shared with mmx, sse registers (xmm), avx registers (ymm), and a truckload of them.
Modern implementations have extremely complex frontends, full of elaborate hacks to get performance despite x86.
Complexity breeds bugs, such as this one.
Then Apple switched to x86, and from day to night we witnessed the magnificent spectacle of the entire Apple fanbase performing a whiplash-inducing collective pirouette towards the narrative that, after all, x86 was not so bad.
ARM did not. There are efforts but they are recent, adoption is bad.
RISC-V, on the other hand, put significant effort into this early on, preventing the situation ARM is in.
Sure, ARMs are better in performance-per-watt game, but the question of how to scale them to the level of high-end x86 desktop processors is still open. For now, I'd argue it's not even clear if that's possible.
So that means that, using the same amount of power, Apple processors -are- faster.
Using the same highest amount of power - absolutely not, unless you could overclock Apple processor and prove that.
Some things just does not scale, if you try to feed 100 amps @ 1.5v to an ARM CPU and run it on 6 GHz, it'll burn out.
It’s a mix of a simpler ISA, good core design, and small process nodes.
AMD laptop CPUs easily compete with or even beat the M chips according to this comparison.
https://www.cpubenchmark.net/compare/5215vs4104/AMD-Ryzen-7-...
It's only recently that other companies like AMD are able to use TSMC's 5nm node process.
But I do wonder, given the other comments here about TDP and these days of thermally-limited performance, what the results are if both are locked to the same constant frequency.
And usually for battery power, it's often better to run really hot for a small ammount of time, that to run for a extended ammount of time at lower clocks.
2. The brand new M2s are only about 20% faster, so the results are still valid.
How is the battery life in practice? Are there laptops with AMD chips which can run all day like Apple's M1/M2 laptops?
The main issue is that AMD/Intel turbo so hard, while Apple clocks their M chips much more conservatively. They are also much bigger, wider designs than AMD (which means they are more expensive but can afford to run slower).
Another is that Windows + OEM garbage + random background apps do so much useless processing in the background. And I'm not even a pro-linux "bloat" zealot... it really is just senseless and unacceptable out-of-the-box.
Modern MacOS is nearly as bad. I upgraded a couple of years ago from a dual core 2016 macbook pro. The machine - even freshly formatted - spent an obscene amount of CPU time doing useless things - like in photoanalysisd (presumably looking for my face in my iphoto library for the 100th time). Or indexing my hard drive again, for no reason.
The efficiency cores in my new M1 machine seem to hover at about 50% most of the time I'm using the computer. I've started to think of them as the silly corner for Apple's bored software engineers to play around in, so the random background processes they start don't get in the way of getting actual work done.
I wish I could figure out how to turn all this crap off. Its no wonder linux on M1 chips is already benchmarking better than the same machines running MacOS, at least on CPU bound tasks.
(That said, OEM bloatware on windows is a whole other level of hurt.)
On the other hand, a low frequency efficiency core is a good place for "bloat" to live. I think thats how Android/iOS remain usable too.
Windows bloat on AMD runs on the big 4Ghz+ cores. And I suspect it does on Intel laptops with E cores too, as Windows isn't integrated enough to know that the Adobe updater and Norton Antivirus and the HP App Store are E core tasks. And even if it does, Intel runs their E cores faster than Apple anyway.
If anyone knows how, I'd love to know.
Don't go complaining when things don't work though. And don't turn things off and forget you did it either.
I instead suggest not caring what `top` says for the day after an OS update. It'll take care of itself.
The advantage there is that Apple knows exactly what HW is running on and can take advantage of every power save opportunity, while on x86 that's much harder.
> High end Intel and AMD chips hold the performance crown but the M chips utterly destroy them on performance per watt. It’s not even close.
I think asking about battery life is pretty relevant.
IMO, real power consumption in joules over the course of a benchmark needs to be the standard when it comes to comparing efficiency.
Too bad there are no bare/unsoldered Apple Silicon chips to try building such boards around. I'm sure, if there were, you'd find them all over AliExpress.
I'd also be curious which of those two boards would have a higher BOM!
[1] https://nanoreview.net/en/cpu-compare/apple-m1-pro-vs-amd-ry...
[2] https://nanoreview.net/en/cpu-compare/apple-m2-pro-vs-amd-ry...
I'm not really knowledgeable when it comes to this, so perhaps I'm missing something.
1: https://nanoreview.net/en/cpu-compare/apple-m2-pro-vs-apple-...
It's also a design that prioritizes perf/watt, whereas CPU vendors tend to prioritize perf/area. (aka perf/$)
Apple's M_ Max CPU variants come with a very hefty price tag though.
Power consumption scales non-linearly with clock speed. So you're comparing two variables that are dependent on each other. If you want a meaningful comparison, you have to align one of those variables. As in, either reduce x86 to M2 Pro/Ultra/Whatever's power budget and then compare performance, or align performance and then compare power.
This is especially true for the desktop class CPUs where outright performance is the name of the game at all costs. AMD & Intel are constantly throwing upwards of 50w at an extra 5% performance, because that's what drives sales - outright performance.
The difference in engineer years in designing and testing a complicated x86 chip that works correctly versus an ARM chip, however, are pretty big.
The answer is no. The question of how to scale them to the level of high end x86 desktop processors is absolutely not open. It’s clearly a solved problem.
The xmm registers are the low 128 bits of the ymm registers. So you're left with three register files, consisting of 8, 16, and 16 registers each. The only thing out of the ordinary there is the x87 register state, although maybe you'd consider the unusually small size of the register sets as out of the ordinary nowadays (e.g., RISC-V and AArch64 each provide 32 registers in their two register files).
And is not implemented on the chip in question, making it a irrelevant for considering the complexity ostensibly leading to the hardware bug under discussion.
Internally CPUs have large register files and register renaming circuitry anyway, so I suppose everything is shared with everything else, except maybe ESP and EBP.
Interesting to see such big leaps in CPUs still happening. Popcorn!
M1's integrated memory is completely generic LPDDR5. It's the same stuff the rest of the industry uses, there's no power savings here (and it's not any more "integrated" than AMD & Intel have been doing for half a decade or more, either)
The primary interesting thing about the M1/M2's memory is the width of the memory bus, which is how it gets such huge bandwidth numbers. But if anything that's costing power, not saving it.
Which means it's still over an external interconnect, which is what actually "takes juice"
> Pushing signals through those big long wires takes juice.
lol no it doesn't. That's a pretty minuscule amount of resistance.
Resistance is proportional to length, yes, but that doesn't make it significant in the given application.
Who the hell came with such a layout.
Is it really this hard to copy industry standard like github?
It's just copied off basic mailing list designs from the 90s (or the 80s?).
That design is basically what happens when you tell a kernel dev to write a mailing list archiving UI. It's clean because they value simplicity, but they obviously have ~0 non-CLI UI/UX experience.
See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/lin... https://lpc.events/event/11/contributions/983/attachments/75...
Although the fact that there apparently exist some APUs that have not had the update applied because of shitty OEMs is very concerning.
One of the fundamentals of selling shit profitably, is that you try to sell the vast majority of what you make, one of the consequences is that the vast majority of users exist outsider of your company and after development.
So you throw some very smart people at the problems of building and validating and building and validating, and hope that no two of them makes or repeats a mistake.
Yes, there've been some disturbingly cavalier attitudes on the patchable software side towards release quality, and more recently by Boeing on the hardware side (which they proceeded to patch from the software side), but I have not seen that sort of wanton disregard for quality from AMD/Intel/NVidia.
Honestly, the fact that this is even interesting enough to show up on HN tells you enough about how frequently it happens.
Edit: @empyrrhicist: ah, my mistake. I misunderstood, thinking more recently manufactured CPUs might come with updated microcode. Thanks for the quick help.
I'm not that familiar with the details of recent CPUs, but at least on the Intel side, I believe they do as part of the stepping identifier.