Hacker News Reader

Comment by BulgarianIdiot | Hacker News Reader

Wait, so your thesis would've led to no FPU, GPU, hw TCP, etc. We just slowly and linearly chug along with a classic 8086 beautiful ISA.

Well, the beautiful (not so beautiful these days) ISA is always there for you, while we grab a library to use a suitable specialized processor and run our shit 1000x faster for 1/100 the power.

View on HN

yes. It's a naieve world view, I fully admit. bolt on co-processors are just a fact of life. Mostly, we now run in abstractions "above" this layer of concern.

I feel like this about the TPU and other chips bundled into phones too. I wonder if we're going to wind up with "photoshop specific" bolt on architectures.

So at what point does something become special purpose? Is L1, L2 or L3 cache special purpose? What about io chips? What about the firmware inside ethernet cards, harddrives or the video chips (not even talking about GPUs).

I'm not trying to be combatitive, but it seems completely arbitrary where one would draw a line and taken to the extreme one is essentially left with a CPU and possibly some RAM that might be some ideal computing machine, but can't even talk to the outside world.

On chip to me, is integrated. but with multi core. shared facilities on the die are a bit of a bottleneck sometimes (I don't do this for a living, thats how I understand it)

So the whole 'hyperthreading is cool, 2x the CPU' thing: it turns out that as long as your e.g. integer only, true. If you invoke FP, not true: they stall.

L1 cache in some instances is now big enough some people's code never leaves it.

Nobody who lives above a compiler should ever have to worry about this. I live above scripts. I don't really worry about this. I just hark back to when I ran these boxes, on raised floors, remembering how .. distasteful adjunct computing equipment was. It was completely asynchronous, required it's own resets, interfered with cabling, had effects on the bus (unibus!) you didn't entirely understand, they made life "harder" for operations.

Did they speed things up? Sure!

Funny, in this light, GPT-3 accelerator is like strapping a cache of the entire internet and knowledge of humanity to your board.

GPT-3 might be the ultimate contender for https://en.m.wikipedia.org/wiki/Hutter_Prize - now if we could only find the prompts to recover it all

>one is essentially left with a CPU

CPU? Ooh you lucky, lucky sod. Back in my day, you wanted an OR gate you had to string some NANDS together.

I remember a rather interesting "application specific" thing that happened with Risc PC's in the UK. Because at that particular point in history Acorn and the RISC-OS ecosystem were having to coexist with the Windows ecosystem, people wanted to run their DOS and Windows applications on their Risc PC's. The 80386 and 80486 were bolted onto daughterboards and sold as special-purpose add-on processors, just to run those applications.

I wonder how you feel about secure enclave chips

There a sort of necessary evil. They definitely complicate things, look at the debates over Tannenbaums work writing the os for secure enclave bios interactions. And, like protection rings they come with questions about bugs and subverted state.

I have worked on systems doing HSM like activity which depended on vendor specific TPM. They're a pain.

Reply on news.ycombinator.com