Reverse-engineering the interrupt circuitry in the Intel 8086 processor
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The 8086 has some strange characteristics, such as acknowledging interrupts twice, but these features make more sense when looking at the 8086's history and what it inherited from the 8008 and 8080.
The "real" next gen processor was supposed to be iAPX 432 but due to delays they needed a stopgap, thus the 8086 was born in a hurry... so anything with high risk was off the table from the start. It was never going to get rid of segmented memory though believe it or not they added GP registers compared to the 8080.
Funny how iAPX 432 would not be the last time Intel tried to set a new standard for CPUs nor the last time they tried to rely on sufficiently clever compilers.
All of the above mentioned CPUs suffered from trying to be suitable for desktop calculators and/or prioritizing assembly language conveniences. iAPX 432 tried to partially implement garbage collection in hardware.
Even the venerable 286 and its broken protected mode was designed for industrial systems - Intel never intended it to be used in a general purpose PC which may explain some of its quirks.
Similar in time to the playstation ASICs (and similar design in sort of a soup of standard cells on a CMOS process), but at a gate count similar to Ken's fantastic work here on the 8086 is the work reversing the Gameboy SoC: https://github.com/furrtek/DMG-CPU-Inside
Chip manufacturers, professional chip reversers, and academic institutions have the tooling to take chips apart at varying levels of granularity all the way down to atom by atom if necessary.