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Comment by Salgat | Hacker News Reader

If you take a Zen 3 running at optimal clocks for efficiency (such as the 5800U) the difference between its computing performance per watt is competitive with the M1 if you account for the difference in node size (which TSMC claims gives 30% less power consumption at the same performance). As the article points out, the real efficiency gains will be domain specific changes such as shifting to 8 bit for more calculations.

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It really isn't competitive.

First of all, when you downclock anything, you're going to gain efficiency. If Apple downclocks M1, it can get even more efficient.

Second, most of these tests use Cinebench, which is highly optimized for x86, not ARM instructions. Geekbench should be used instead.

Third, the M1 is a SoC. Everything is on it. Everything is efficiently connected directly inside the chip.

Both the M1 and 5800U run around 15W and are already clocked for efficiency. The M1 Max is their higher clocked less efficient offering.

This is false. The 5800U will boost well beyond 15w. Ignore their TDP marketing ratings.

How would x86-64 be as efficient with the same transistor & power budget when they have to run an extra decoder and ring within that budget? Seems physically impossible.

My guess is it's related to the higher transistor count. The M1 for example has 16B transistors compared to the 5800U with 10.7B.

As I understand it, the actual processing part of most chips nowadays is fairly bespoke, with a decoder sitting on top. I doubt decode can make up that large a portion of a chips power consumption (probably negligible next to the rest of the chip?), so other improvements can make up for the difference.

I found this to be a pretty expansive answer to this question: https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-...

Thank you for the detailed article!

All else being equal, they can't. But the difference isn't as big as some people like to think. For a current high end core, probably low single digit %. And x86-64 has had a lot more effort going into software optimization.

Because the more complex decoder is traded in this case for a denser instruction set, which means they can trade it for less instruction cache (which is more power hungry).

How can AArch64 be as efficient when it implements all of the old 32-bit extensions?

Some don't, but a phone does.

The latest ARM Cortex CPUs (models X2, A715 and A510) drop 32-bit support. Qualcomm actually includes two older Cortex-A710 cores in the Snapdragon 8 gen 2 for 32-bit support. Don't know much about Apple Silicon but didn't they drop 32-bit a couple of years back?

Google has purged 32-bit apps from the official Android app store, but as I understand it the Chinese OEMs that ship un-Googled AOSP ROMs with their own app stores haven't been as aggressive about moving to 64-bit.

Apple also entirely drops 32-bit from their arm systems

The decoder has negligible power consumption and die area on a modern CPU.

Not if you have a complex ISA like x86 and want a very wide decode.

yes if you want to keep the transistor count low

M1 has 16 billion of them

AMD is below 10 billion

> when they have to run an extra decoder

it's not that expensive

it's a tradeoff, you lose something there, you gain somewhere else.

x86 has a more complex decoder exactly because it was less powerful and had to save on computing power and energy consumption, not being a mainframe.

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