High performance RISC-V CPU
ventanamicro.com
ventanamicro.com
This CPU solves this by making the instruction cache very large. This certainly requires more fetch stages in the pipeline to clock high, which is offset by the simpler decode, probably giving similar results to competitors.
RV64GC is the most dense 64bit architecture. This means it takes the least bytes of code to do a given task.
You are correct that performance is “known” at design time.
That said, as this is a new platform a little healthy “believe when I see it” is warranted not just for the performance of this new chip but also about when it will ship and what it will be competing with by then.
It looks very promising though.
https://www.nextplatform.com/2023/02/02/the-first-risc-v-sho...
Theoretical, or not.
Also the headline: The First RISC-V Shot Across The Datacenter Bow
/me morphs into Dark Fader and intones: I find your lack of enthusiasm disturbing… … …
I think the same may happen with smartphones/TVs/tablets/etc. Billions of these devices are sold each year, compared to perhaps tens of millions of high-end desktops or servers.
If you are thinking of a tower though, there may in fact not be any. That is more of a statement about this desktop market than the RISC one though.
https://cdn.statcdn.com/Statistic/270000/272595-blank-355.pn...
Plum forgot about the iMac.
If you're going to add your own instructions anyways, then why go risc-v over arm?
Their success with M1 and M2 aren't hugely generalisable.
Even for RISC, you can buy some boards but I assume those don’t count. But at a regular consumer level, there’s tons of ARM computers in use right now, even if they’re restricted to only a few companies who make them.
RISC-V I don't know about, but having fixed length instructions is theoretically safer.