Iirc caches mostly exist to help keep pipelines full. You could maybe imagine an architecture with deterministic memory access times from specified regions.
By the 2nd or 3rd generation, Intel had made some changes that really improved performance a lot. Was the final generation of Itanium the 4th generation?
You can find out by disabling the stride prefetcher and observing the 90+% performance regression in all your software!
Sure.
But it's very easy to level down. And almost impossible to level up.