I recently came across https://makerchip.com/, and the TL-Verilog language it supports looks useful for when you want to make a pipelined design later.
In short, you can define generic reusable flow constructs like stall and backpressure pipelines. You can then instantiate them and slot in your logic, and signals will be automatically pulled through the different stages and pipelines as needed. The example at this part of the video shows then how adding something can be a two line change when it would be hundreds of lines if you were working at the RTL level: https://youtu.be/hQ6HhOBHKy0?t=2581