I guess that's nonsensical. 1-bit in all FP is the sign bit. So I guess the minimum size is 2-bit FP (1-bit sign + 1-bit exponent + 0-bit implicit 1 mantissa)
I guess that's nonsensical. 1-bit in all FP is the sign bit. So I guess the minimum size is 2-bit FP (1-bit sign + 1-bit exponent + 0-bit implicit 1 mantissa)
https://medium.com/ozonetel-ai/compressing-bert-sentence-emb...
FP3 gives you sign, 1x "exponent", 1x mantissa, so still kinda bit packing.
I could see FP4 with sign, 1x exponent, 2x mantissa. Exponent would really just be a 4x multiplier, giving +/-0,1,2,3,4,8,12
Or invert all those, so you are expressing common fractions on 0..1
EEs would recognize these values to be the Preferred Resistors values for projects (though more commonly the E6 series is used in projects, the E3 and E1 values are preferred)
That's 3 values per decade, which is slightly more dispersed than a FP4 that consists of 1 sign + 3 exponent + 0 (implicit mantissa 1 bit).
Or the values -128, -64, -32, -16, -8, -4, -2, -1, 1, 2, ... 128.
Maybe we can take -128 and call that zero instead, cause zero is useful.
--------
Given how even E3 is still useful in real world electrical engineering problems, I'm more inclined to allocate more bits to the exponent than the mantissa.
Took me until today to realise that sequence is a rounded version of 10^(n/3) for integer n.
And exponent seems to be much more important for these small sizes. The first paper that shows up for FP4 almost has negative mantissa bits. Their encoding has 0, 1/64, 1/16, 1/4, 1, 4, 16, 64.