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Comment by bfrog | Hacker News Reader

I tried Verilog at first but found myself liking vhdl quite a lot more. It just fit my mental model better and helped avoid some really silly errors I kept making as a beginner.

I could probably pick up Verilog now a bit quicker, I’d jump straight to system Verilog though if I did.

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Verilog does make it fantastically easy to create bugs! It feels like very early C versions that are way too lenient. The biggest bang-for-the-buck you can get here is adding "`default_nettype none" at the top of every file, which makes undeclared identifiers an error. I believe this is SystemVerilog, though, and I agree that's what you should learn.

The default_nettype directive is at least in the Verilog 2001 standard.

Ed. Seems it's in Verilog-1995, too: http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_r...

You should try out Chisel. I learned and used VHDL first, but after switching to Chisel I realized it was much better designed and avoided many of the footguns you'll likely encounter with Verilog or VHDL. And in general, it is a joy to work with.

I like the idea of a newer language but inevitably it feels like anything not Verilog or vhdl is missing direct tooling support from the vendors.

Do any vendors intend on supporting chisel? Does chisel have enough control to ensure generated vhdl/Verilog match the what vendors look for to infer certain things like certain ram and dsp instances? Does chisel have a fast simulator like ghdl?

Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators.

I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...

I haven't used Chisel yet but looking at the home page it looks like it generates surprisingly readable Verilog with source mapping.

Also there's a project called FireSim that can do cycle accurate simulation of Chisel on cloud FPGAs apparently at 10-100MHz which is pretty crazy!

SystemVerilog or a modern language like Chisel/HardCaml is the way to go. Combine SV with a good linter and you can avoid most of the silly bugs the language lets you do.

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