Self-Modifying FPGAs?

I'm working on the problem of "getting it into the fingers". For example, if you learn typing you start by repeated muscle motions which you gradually learn. A similar thing happens when learning a musical instrument or woodworking.

In order to do this form of "finger learning" I start with a state machine encoding the initial actions. A JIT-like mechanism recognizes repeated actions, collects up the sequence, optimizes the total sequence, and then creates a new additional state, thus "getting things into the fingers".

Ideally I'd like an FPGA that could dynamically self-modify. It would be able to change lookup tables (LUTS) and pathways within itself, thus changing the recognized state logic.

The only path I know about would be to change the RAM that holds the initial state and then reboot.

That path requires deep knowledge of the binary blob that gets loaded when creating the FPGA design.

Changing that binary blob, as far as I know, involves going back to a Verilog compile and then through tools to do place-and-route, etc. This tedious path is my current effort.

So the question is: Is there an FPGA capable of directly self-modifying by writing LUTS or by writing RAM?

Ideally this self-modifying FPGA would have an embedded hard processor (RISC-V) that could read/write LUTS and pathways in the rest of the FPGA. The hard processor would run self-aware tasks like the JIT.

I know Intel has a CPU/FPGA combination (only available to data center scale vendors unfortunately) that MIGHT be able to self-optimize repeated instruction paths. This might be difficult on an X86 architecture but it might be reasonable on a RISC-V architecture which allows non-standard instructions.