> the 8088 has a 4-byte prefetch queue instead of a 6-byte prefetch queue
My whole professional life, I've been led to believe that an 8088 is just an 8086 with a tiny state machine bolted in front of the bus to split multiword accesses. That it has design differences is really surprising. If the prefetch queue is smaller, then... what are they putting in that die area? Or did they redo the layout in other ways?
It was easy to measure the length of the prefetch queue by a self-modifying program, which replaced the instruction placed 4 bytes after the current instruction pointer.
On an 8088, the new instruction was executed, while on an 8086 the old instruction was executed.
Various other such obscure differences (e.g. the value of a pushed stack pointer or the result of a shift operation with a shift count greater than the register size) were used to identify NEC V20 and V30, Intel 80186, 80188, 80286 and 80386, because architectural identification means, like the CPUID instruction, have been introduced only in Intel Pentium and in the late 486 models that were launched after Pentium.
It became hard on the 386, as linked in the article: http://www.rcollins.org/secrets/PrefetchQueue.html
Coincidentally a topic I did some reseach into recently. It appears to be in both the Pentium(P5/54) and PPro(P6), but not the 486.
For detecting 8086(/88) and NEC V30(/20) vs. 80186 and anything later, I'd recommend using a shift instruction with a count of 33. The 186 and later processors will mask it with 0x1F, resulting in a shift by 1 instead. A shift count of 32 would also behave differently, but not set any flags because a shift by 0 effectively becomes a NOP.
This is true even on x86-64, only for 64 bit operands is the count masked with 0x3F.
The 8086 didn't have that problem, because it only started a new prefetch when there were two bytes free in the queue, so there was enough time for the jump microcode to stop it.
edit: already mentioned in the article