Ripes: Visual computer architecture simulator, assembly code editor for RISC-V

As someone in the risc-v education space, it has been very cool to see RIPES develop. It seems like I blinked and it gained a lot of features. It gives you the most information about how a program might run.

If you would rather focus on the software and you want to try learning risc-v assembly, I would recommend the simulator I made https://github.com/TheThirdOne/rars .

This is the tool I needed while taking the computer architecture series in college. An animated simulation would have gotten me up to speed much faster. Working through each instruction using a pencil and paper was a slow process that would have been more beneficial after seeing a simulation run a few times.

Might one do a cache-aware code competition? Given the simulator's determinism and cache.

As attention to cache-friendly data layout seems often lagging its importance ... err, and the world doesn't yet have enough premature optimization.

Implement this algorithm; it will be challenged with <large n> input sets; here is a training set generator; your competition set runtimes will be aggregated with <metric>; minimize it.

Does anything like this exist already?

This is super cool! I have not had time yet to play with it properly but just running some sample code and watching the animated stepping is insanely nice and very educational! Thanks.

Wow.. there's just one principal author who has written almost all of it. Very impressive!

This looks great! Would be interesting to make custom processor models for this

This is great for teaching, thanks for sharing!

Great tool and kudos for it being native.