AMD, Intel, and Nvidia Reportedly Slash Orders with TSMC
tomshardware.com
tomshardware.com
Sounds like it might not be such a big deal for TSMC, at least in the short term.
Unfortunately, this likely means more shortages and costs stay high for the consumer.
Intel's new Arc product is the first competitor from another company in a very long time.
GPUs are insanely complex and the drivers are full of hacks (even per game basis, a driver could swap shaders with ones written by Nvidia/AMD if it detects you're playing the newest popular title). The threshold to enter the market is incredibly high.
Intel is hitting that problem head-on; no game is written to take advantage of its new GPUs, and has to suffer a ton for it. It's not a guarantee Intel will ever be able to escape this problem.
Companies like TensTorrent, Graphcore and Lightmatter (for example) try to hit different spots of the architectural landscape (seemingly all optimising for 'cheap to tapeout' in all sorts of clever ways, but you still have to code for it (even though you often get python APIs and deep learning tensorflow/torch support, but that's probably not getting you to to max perf). Very interesting to watch, and hopefully one can get their hands on that kind of hardware and build a community around it.
We really need the forces that be to change this.
Power regulators doesn't need small transistors, it wants big nice and fat transistors. You'd get at least one of them in every device and a bunch in any bigger device. Same with any power device, LEDs, and really anything that passes some current.
Any microcontroller smaller than "runs full fledged linux" often cares about cost of production first and foremost, hell, STM32 only recently [1] got on 90nm node!
Interestingly enough, bigger node might get you worse uA/MHz but often lower idle current (the bigger things are the lower the leakage) so they might even be desirable. And the chip might want to have some mA current output on each pin (so it doesn't require external drivers to control stuff), which again means some transistor size in your I/O port is fixed and can't be made smaller so your savings from going to smaller process are not linear.
For vast majority of non CPU/GPU chips it comes to cost to manufacture and those 20+ years old lines not only paid for themselves multiple times, they also have great yields.
STM32G0 is value-oriented.
The latest-and-greatest power efficiency STM32 is the STM32U5: https://www.st.com/content/ccc/resource/sales_and_marketing/...
Which seems to be 40nm.
I'm not 100% sure if the STM32U5 is the smallest node they're using. But 40nm (or better) seems like a safe bet these days.
Is it possible to make bigger transistors using a smaller process? Just because you are using saying a 7nm process, can't you still make a transistor (like if you needed) that was the same size as it was on 90nm? I think of newer processes as merely being more precise so you could still do the old designs on them, you are just unecessarily tying up the newer machines... but concievably in the future you could just start using 5nm process to keep producing 30 nm and 90 nm chips just to consolidate production lines, non?
I know nothing about this, so I'm just asking.
5nm is extremely inefficient to make: IIRC, you need to submerge the parts in ultra-pure water and blast it with a ultraviolet laser to get down to 5nm. This is because even ultra-pure filtered air has too many particles that disperses the laser that you're off by a few nanometers... ruining the design. Filtering all that water and powering ultraviolet-spectrum lasers is extremely high power / electricity usage.
In contrast, a 40nm process is still airborne. You can largely do 40nm with "more standard" equipment. No ultra-pure water needed. No ultraviolet lasers. No quad-patterning. You can use "regular" light, with "regular cleanroom air", and "regular" processes to make the design at far, far lower costs (or at least, with less electricity).
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IIRC, the "ideal" cost-efficiency moving forward is to rebuild our older fabs for 300mm wafers, standardize upon that wafer size. Older fabs were standardized on smaller 200mm wafers with only ~45% area of the bigger wafers (and less in practice, because the edge of a wafer has all sorts of inefficient issues involved).
There's also the issue that a lot of these designs, such as Power MOSFETs, are... just one, maybe two, transistors. If your transistor is like a centimeter in size, there's no point using 5nm or 40nm or even 90nm nodes on it. There's just much much cheaper ways to fabricate a "centimeter-sized" MOSFET. There's all sorts of application of "chips", from 1-transistor Power MOSFETs to ~100 transistor op-amps, to ~10,000 transistor transceivers, to 10-million+ transistor NAND-Flash arrays. (1 Megabyte isn't much these days though, lol)
5nm is a multi-billion dollar fab, absurdly high running costs, and very expensive wafers.
As a data point: 5nm lithography equipment is > $100M/unit, needs megawatts of power to run, and they handle about 60-80 wafers per hour.
90nm lithography equipment is ~ $1M/unit, needs kilowatts of power to run, and they handle about 60-80 wafers per hour.
So a wafer scanned on 5nm equipment that could have been scanned on 9nm equipment is carrying a very large capital and operational cost burden that's pointless.
This allows for power saving because you don’t have to condition signals as they jump from silicon piece to silicon piece (oversimplification).
It is somewhat harder to make the above on smaller nodes than it is to make just processing cores or just memory.
That fact (in addition to a number of other cost and technical factors) is why microcontrollers lag process nodes.
I'm not convinced this is the reason because the microcontrollers I know of use SRAM not DRAM and SRAM is what CPU caches are (plus of course some extra logic for the cache management aspect). I am aware that designing dense and power efficient SRAM for a cell library is considered a pretty hard thing to do, but it seemingly has already been for modern processes.
But they are not optimized for low idle current , they're for motor control and led driving.
https://www.tomshardware.com/news/tsmcs-wafer-prices-reveale...
When I worked at Samsung, flash & LSI were like 2 different companies. Lots of reuse at the systems engineering level though. At a certain point of abstraction you can't tell what is on the wafer anymore so you might as well track it in the same database.
Will that capacity be utilized by other companies? E.g. what is preventing a RISC-V company from leap-frogging the competition?
They would need to have already taped out on N7 and be ready to start mass production now. That doesn't happen overnight. Even if you have taped out a ready-to-fab design, you usually want to start small and run a few rounds of QA on small batches of chips before you start ordering enough wafers to make a dent in TSMC's schedule.
So those companies would probably be targeting something in the range of 14nm to 10nm in order to take advantage of the fire sale on late DUV tooling to prove that they can make a working chip to investors, and then leapfrog to N5 after the giants have jumped to N3.
In other words, the slowdown?
Don't know where you got that info but that's definitely false.
If you look at Nvidia's lineup, each GPU has a die that's unique to that product in both size and markings. Sure, there have been/are a few products that make use of the same die but with defects depending on yelds, but those are usually in the same performance class (1070, 1070TI and 1080 had the same die), and not the case you're talking about of entry level GPUs being high end GPUs dies with defects fused off. That's never the case. An RTX 3050 die is a completely different part than a 3080/3090 die.
https://arstechnica.com/gaming/2022/09/the-end-of-ethereum-m...
Really awesome charts here-
I do think crypto is demand destroyed due to their own collapse unrelated but related to the economy in general. My expectation is that the next crypto bubble will take longer to inflate this time vs the last, but hell what's the point reading tea leaves. This could be the end of crypto. All we need is a new and exciting meme way for early adopters to sell losing bets into ignorant followers.
I think this is less about consumer GPUs and more about cost cutting in big corps slowing expansions, and the reduction in crypto demand.
Think about every tech company that says “oops we overbuilt for covid, whelp let’s lay everyone off” well they could be buying fewer servers if they over-anticipated their needs in that department too.
You were unable to convince your executives to adopt huggingface, IOT, and instead they opted to employ phone calls and Excel spreadsheets.
You, consumer, failed to accept Stadia into your heart,... and now you shall pay for your snide indifference!!
Of course real consumers can't buy the hardware, real consumers don't have AAA credit ratings.
You can always eBay a K80 as well if your motherboard supports the >4G decoding switch, but my primary point was about the insane purchasing power that affords large CommSvc sector company the ability to crash the market for a product before anyone even has logistics in place, apparently wishing to gatekeep any applications.
- Game devs haven't made any games that stress a cloud gaming environment, they didn't even push VR.
- Corporate consumers are hardly adopting AI at all, because there's still barely even a workforce.
- Some very vocal people find proof of work a distasteful mechanism to support logistical metacommodity growth.
It doesn't make much sense for NVidia to increase production of 4xxx series when there's so much 3xxx series sitting around in warehouse inventory.
Unless you're willing to spend $1000+ the real world performance differences aren't even that large: https://www.videocardbenchmark.net/high_end_gpus.html
Semiconductors are so complex and capital intensive that even a duopoly couln't balance the expense.