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Comment by yazaddaruvala | Hacker News Reader

> 3nm technology would feature an estimated 60 percent gain in density of logic transistors and reduce power consumption by 30 percent to 35 percent at the same rate compared with 5nm technology

I'm really looking forward to the new Gravitons and the M3 Pro/Max/Ultra MacBooks! and what they will be able to achieve.

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Smaller transistors does indeed reduce dynamic power consumption as transistors can switch with less charge, however the leakage current (static power consumption) will rise, more than the already significant amounts. I'm not sure how much actual energy savings will come from this in an application like laptops.

Also, increased density isn't a huge deal as, while it reduces the die size which reduces the cost, it also likely costs more than an already mature process. It can help with increasing the amount of logic gates in series before needing to be pipelined to the next clock cycle, but that's not that big of a deal either

Leakage power will rise all else being equal, but there are plenty of things designers can do to counteract that for reasonable costs.

Reducing logic density will still allow for lot's of more SRAM for a chip of the same size. Even if SRAM won't scale. More SRAM is almost always a cheat code for squeezing more performance out of a design.

Logic and SRAM are completely different things in this context. SRAM actually has had almost zero scaling since N7 while logic has more than doubled in density (2x theoretical / 1.5-1.6x real-world shrink at N5 relative to N7, for example, and then N3 gives about 30% real-world shrinks to logic, although that’s less than expected and the good shrinks are going to come from the later N3E node).

As a result we will probably see the pendulum swing back from cache-heavy designs. Going ham on cache was an obviously advantageous strategy at 7nm, you can basically look at it as N7 having been two full node families ahead of the curve on sram density (Samsung is only catching up at 3nm/2nm). But since SRAM hasn’t scaled at all in the last 2 nodes it’s becoming comparatively more effective to spend your transistors on logic instead. You still want big caches of course (and cache can be easily stacked ala AMDs v-cache) but it’s more worthwhile to spend more heavily on logic than it was on 7nm.

I doubt this will happen. Cache is way too important. I would be very surprised to see chips with less cache in the future. I guess we will see in 10 years where the industry has moved. Currently a LOT of the transistor budget is blown on things we don't really need.

Any specifics on what you think transistors are being wasted on?

Mostly SoC related features. Look at the M1 for example. The budget allocated to a DP controller is HUGE. That doesn't have to be on the SoC chip and can be externalized.

Yeah, I don't think we'll see reductions in cache, that's always a hard thing because software comes to expect it and can be hurt by reductions, it's kind of a one-way ratchet. But we'll stop seeing the huge increases gen-over-gen, at least on the primary die. Additional transistors spent will probably mostly be spent on logic rather than cache.

N7 basically was the era of "let's throw cache on everything, even products that traditionally haven't had caches". GPUs never had L3 cache before, for example, but that became advantageous, even in GPUs, which are focused around logic/computation rather than deep cache structures. And now you are seeing that train grind to a halt - RDNA3 did not expand the cache further, although they did increase the bandwidth of the cache (2.7x higher, although bear in mind that RDNA3's memory subsystem is 50% wider which means cache bandwidth is effectively 1.8x higher in a relative sense).

Similarly Intel went completely nuts once they finally got to a 7nm-tier node (Intel 7 aka 10ESF). Raptor Lake in particular is just caches all the way down...

Since cache no longer shrinks at 5nm and 3nm, but logic does, it makes sense to do some logic-intensive things rather than just throwing all your area at cache like 7nm.

On the flip side though, since cache can be pulled out to a separate cache die fairly effectively (AMD v-cache), you can continue to scale cache there. RDNA4 and NVIDIA Blackwell are both rumored to be coming fairly quickly which suggests a potential respin. And both AMD and NVIDIA have things they need to work on, NVIDIA doesn't have DP2.0 and AMD seems to have screwed up RDNA3 fairly badly, so a "similar but improved" quick refresh makes sense. Rumors mentioned "[NVIDIA] Ada Lovelace with a stacked cache die" at once point and imo that is very plausible for the next-gen Blackwell chips as a potential quick-fix improvement to keep scaling Ada.

But I think we're going to see an overall trend towards "the logic die is for logic and L3 cache gets stacked on top" for now. That seems to be a formula that works without too much trouble. L1 and L2 on the logic die is unavoidable, there is too much incentive for proximity/latency improvements, but big stacked L3s seem very effective and doesn't cause MCM-style problems.

Yes if cache can be stacked I can see it happening. But I thought this is AMD exclusive tech and other aren't allowed to replicate it.

I don't think there's anything AMD-exclusive about cache stacking. It's made possible with TSV (through-silicon via) and direct bonding (ultrasonic or Cu-Cu bonding) to make the movement energy very low. You just bond the second die into some via you've left in your main die, it's relatively straightforward, just an evolution of the same HBM/HBM2 principles but with cache instead.

Going forward there will also be non-cache (and non-memory!) things bonded as well.

I just don't know what is left to achieve really. I have an M1 pro and I just don't really hit any bottlenecks in my workflow as is (unless I am building some obscenely large legacy codebase)

It just seems to me that we are hitting a point of diminishing returns in terms of CPU performance because honestly, the speed of my laptop could triple and it would not noticeably affect my experience in any way.

The main areas of improvement that I would actually notice are better battery life, and faster RAM and SSDs (faster networking as well)

Better battery life is equivalent to more efficient power consumption (that the 3nm process improves on).

This is more GPU than CPU, but I want to infer 3D models from my security cameras in real time so I can do some CSI "turn left and look behind it" shit. And use the overlapping textures for superresolution so I can shout "enhance!" and read the license plate reflected in the perp's eyeball.

As for reading e-mails and so on, yeah, we've pretty much reached peak e-mail.

If you can’t do that stuff right now with today’s CPUs, in sub-realtime, then throwing more/faster CPU at it won’t make it possible.

I haven't described anything that can't already be done (well, reading a license plate in an eyeball was mostly an exaggeration). It just can't be done affordably in real time on a home computer. And it's just the first few out of many examples to come to mind.

I think people fall into the trap of conflating "this is what I do with my computer" with "this is what my computer is for." Obviously if computers are only for doing the things you can already do with them, then they won't benefit much from improvements.

> I just don't know what is left to achieve really.

Just use your imagination a little bit.

Unless you think your current workflow and the tasks you use your machines for are the pinnacle of what an individual will ever be able to accomplish?

Currently there are so many things that are so computationally intensive that they can only be processed on server farms that only the Googles and Amazons of the world can afford.

I am a YouTuber, and I spend a significant amount of time editing and rendering video. My main laptop is a full-spec M1 Max MacBook Pro, and when I'm home, I work on a full-spec M1 Ultra Mac Studio.

Both computers are extraordinarily fast, but I still spend a lot of time waiting.

I would be willing to spend a lot of money:

(1) to reduce that time, (2) to significantly increase my laptop's battery life, and/or (3) to significantly increase the size of my laptop's already-rather-gargantuan 8TB SSD.

Maybe I should become a programmer. Sounds like there's less waiting :P

> what they will be able to achieve.

Who? TSMC and Arm?

And Apple will take all the credit for TSMC's achievements, as usual.

You do realize that TSMC is heavily bankrolled by Apple right?

Who has the details of this strategic relationship?

Remember Apple's infamous $200 billion cash-pile during the peak iPhone era of 2010-2016? How much of it went to TSMC?

They are currently just under $50 billion and have bought back $130 billion+ in shares since 2018 I would most if not all of their reserves went into buybacks.

And ASML will remain in the shadows

So will Zeiss

ASML has a market cap of $227B, and is 37th in rankings of market cap worldwide. Hardly in the shadows.

TSMC is in 12th at $395B.

For curiosity’s sake, Zeiss is #1,327 at $11B. Not bad though, P/E of 41, so market thinks it has quite a future.

https://companiesmarketcap.com/carl-zeiss-meditec/earnings/

To be fair Intel and Samsung are also ASML EUV customers.

Apple is one of TSMC's largest customers. Their presence in the market alone shifts how TSMC designs its processes and does business in general.

I don't think TSMC gives a hoot about "who takes credit" considering how much $ they're getting out of this arrangement.

Apple chose to use N3, AMD chose to use N4, and Intel chose to use 7. I think it's fair to give Apple credit for making a tradeoff that leads to a better product.

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