Ask HN: Reading on esoteric side of “tick-tock” silicon business strategy? | Hacker News Reader

Ask HN: Reading on esoteric side of “tick-tock” silicon business strategy?

2 pointsentrepy1233 comments

Question: Can HN please recommend specific things to read to understand any potentially lesser-known but interesting history of the "tick tock" strategy famously used for silicon chip improvements and rollouts for the past decades?

# Background

The popularly known version is something along the lines of: like clockwork, CPU improvement cycles consist of "tick" (shrink the architecture a little), then "tock" (improve the architecture), then repeated.

This obviously resulted in a long term trend of upgrades and capability increases.

# What I want to know

Is there documented history from the silicon industry of esoteric or lesser known business and engineering stories about "tick tock"? Specifically, could it have been possible or at least discussed to "move ahead" more rapidly, but instead, it made (far) more business and political sense to inch things along?

# Notes

- I anticipate a popular refrain saying that you have to innovate little by little, by the very nature of the improvements.

- I also anticipate that even a "broad and deep" traditional understanding/education of computer engineering and its history might not uncover this particular topic.

- Searching the web, it is sort of hard to find coverage of this exact topic I am looking for, even just to understand it better broadly.

Does HN understand the question, and, if so, has this topic been covered somewhere? Any books, oral histories, articles (academic or general), websites, or even documentary videos on the subject would be appreciated.

Thanks in advance!

# Aside/clarification

This question is only really about the hardware/chip/CPU aspects. There are related issues in software, systems, augmentation, etc. that I understand somewhat more about regarding issues of "missed/impossible leaps" and computer-human evolution/uptake, but this question is not about those issues really.

EDITS: 1) Minor wording update to specify focus area more clearly. 2) Improved formatting for readability.

The big story is that improving manufacturing nodes has had diminishing returns since 2005 or so.

The great revolution in personal computing performance came when the IBM PC got thoroughly entrenched. Unlike the other 1980s micros, the CPU clock was not locked to the video system so it was possible to raise the CPU speed incrementally. Up until 2005 each die shrink meant: (i) more transistors on the die, (ii) faster transistors on the die, (iii) lower power consumption per unit of work and (iv) lower cost per transistor. Note that the miniaturization (i) counteracted (iii) when it came to volume or area power density -- I remember going to a data center around that time which still had some Sun SPARC and IBM Power services and newer x86 servers and the remarkable thing was that the x86 servers were much warmer to be around because they packed so many CPU cores that were working so hard.

When all those factors are in play the next computer you buy will be dramatically better than any computer you've ever owned.

In 2005 the free ride stopped for (ii) so they adopted the secondary strategies of multicore, SIMD, and stream processing (GPU and friends). "Tick Tock" was a thing in this era up until the 14nm process came along. 14nm was seriously late, but 10nm was much later and marked the end beginning of the end of (iv).

Since 10nm was so late it was necessary to keep improving the micro architecture at 14nm (is that "tock tock tock" or "tick tick tick?")

It is getting increasingly shambolic as (iv) goes to its death. Advanced packaging with multiple dies can make up for the slowdown in (i) but it does little to help (iv). So the pattern today is you can buy the best CPU or GPU you ever had, it is twice as powerful as the last one and roughly twice as expensive as the last one. In this market, Intel is decoupling the microarchitecture from the process so they might port a design from 10nm to 14nm or to 7nm, they might even farm the fabrication out to TSMC which means dealing with a whole different set of design rules.

Note that Intel really led the world in CPU volume in the 2000s and 2010s and that meant they could afford manufacturing superiority. Off-brand CPUs such MIPS, SPARC, the DEC Alpha, IBM's POWER could not keep up. It wasn't until the use in smartphones caused the volume of ARM chips to explode that vendors like TSMC pulled ahead in terms of volume and ability and willingness to invest.

You have to remember that the 14nm era was Intel's most profitable, it was no disaster to their top or bottom line in the short term for the development of future nodes being stalled.

Thanks for laying out the context/framework/details! I guess the main question mostly pertains to the relatively speaking easy times period c. 1970-2005, then.

What root constraints drove the maximum amount that (i-iv) could be moved forward with each shrink? In other words, what really governed or capped the magnitude overall rate of change?

I naively/imaginatively wonder if the primary constraint was artificial in a sense, required to maximize long-term shareholder value (or a similar goal). Is this a reasonable query (if not, why)?

If I remember correctly, tick-tock was an Intel strategy and then probably followed by others. Because Intel owned both design and manufacturing, they came up with this lockstep approach to combine design and manufacturing cadence.

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