So the TIA (the Atari video chip) has a "delay" slot for its "player" graphics--a player being an 8 dot wide object - the CPU is supposed to program in new data the player graphics register during the HBLANK portion of the display for each scaline it's visible.
The intention was that the CPU would spend 1 scan line updating P0 graphics, then the next scan line updating P1 graphics, and by setting the delay for P0, both player graphics would appear on the same 2-line portion.
So "2 line kernels" were doing it in a way the TIA supported and providing time to do other things like check paddle status (because you're supposed to be programming a Pong game). Of course the TIA has been wonderfully pushed and twisted in ways never imagined by the designer. I think someone even experimented with interlaced 160x400 graphics.