My academic page list some of my initial publications in this area (mostly graph neural network accelerators for FPGAs): <https://stefanabikaram.com/>. My lab's webpage has way more publications on the topic as well: <https://sharclab.ece.gatech.edu/publications/>. I am just starting my Ph.D. now so my published work is not as varied in this topic yet.

Xilinx's HLS tool is called Vitis HLS, which was created as part of Jason Cong's work, who now runs a dominant research lab in this field (<https://vast.cs.ucla.edu/>). Intel and other vendors have their own HLS tools as well, but I'm not as familiar with them.

Here is one project from my advisor looking at using MLIR for HLS: <https://github.com/hanchenye/scalehls>. The MLIR group itself has its own page here: <https://mlir.llvm.org/>. If you want to see what the internals of an HLS tool resembles, Google's open-source HLS tool, XLS, is availed here as well: <https://google.github.io/xls/>.