The Transistor of 2047: Expert Predictions
spectrum.ieee.org
spectrum.ieee.org
Talk about covering all potential bases.
And “isolinear circuitry” is going to look awesome when illuminated by LEDs in gamer rigs.
There have been developments and startups, see the section on the 21st century [2] for details.
[1]: https://en.wikipedia.org/wiki/Memristor
[2]: https://en.wikipedia.org/wiki/Memristor#Twenty-first_century
https://en.wikipedia.org/wiki/Phonon
https://www.technologyreview.com/2012/08/13/184508/how-to-bu...
Sound waves (phonons) are probably worse
I recall there was a very interesting concept being kicked around a few years ago and I'd love to know what happened to it, but my head is now too full of other technical knowledge that I'm drawing a complete blank.
TLDR:
* Carbon Nanotube Transistors
* Photonics Chips
* Neuromorphic Computing
Also quantum computing of course, but it's probably even further away than these are.
Some form of monolithic 3D is a must to continue Moore's law. Monolithic 3D is different from stacked dies because you make layers of transistors on top of other transistors, instead making them separately, and gluing them together later.
CMOS will transform into something where PMOS, and NMOS part will be combined into one. IMEC already has working forksheet CMOS where P an N parts are sitting side by side. Ideally, N, and P parts will be stacked on top of each other.
All around gates will likely be adopted, either vertical, or horizontal, as they seem to be even easier to do than fins for a given level of performance.
Power will be put onto other side of the die, or buried under epi layer — already in works, and seem to be working well. TSVs will get small enough to use vias to connect individual transistors. Metal routing is getting increasingly more permissive with EUV in general.
New middle-end metals — a possibility.
COAG — already working on latest FinFETs. The metal contact is descended directly onto the gate, rather than on a space near it. All barrier layers are grown directly on top of it as well.
Individual cells will get verticalised as well, and most device development will be done with cells being treated as one device.
We may find a way to put a layer of 3-5 semiconductor on top of silicon wafer to use it for either P or N part of a CMOS device.
Fundamentally new types of FETs are dark horses, and it may well be we may go away from FETs for most high performance comping chips. For always working devices, the relative power efficiency difference of BJT is getting better, and better as device size gets lower. TFETs, and other subthreshold devices can also turn mainstream very fast if people will find ways to work around their inherent issues.